Lines Matching refs:tmp1
83 * tmp1 : %o4 scratch
87 #define SET_SECCTX(cnum, is_shctx, tmp1, tmp2, label) \
91 mov MMU_SCONTEXT, tmp1 ;\
92 stxa cnum, [tmp1]ASI_MMU_CTX ;\
94 sethi %hi(shctx_on), tmp1 ;\
95 ld [tmp1 + %lo(shctx_on)], tmp1 ;\
96 brz,pt tmp1, label/**/3 ;\
100 set SHCTXREG_VALID_BIT, tmp1 ;\
103 or cnum, tmp1, cnum ;\
104 mov cnum, tmp1 ;\
106 or cnum, tmp1, cnum ;\
108 mov MMU_SHARED_CONTEXT, tmp1 ;\
109 stxa cnum, [tmp1]ASI_MMU_CTX ;\
276 * tmp1 = tmp reg
281 #define TTE_SET_REF_ML(tte, ttepa, tsbarea, tmp1, tmp2, label) \
287 GET_CPU_IMPL(tmp1); \
288 cmp tmp1, SPITFIRE_IMPL; \
290 cmp tmp1, CHEETAH_IMPL; \
293 lduh [tsbarea + TSBMISS_DMASK], tmp1; \
298 and ttepa, tmp1, tmp1; \
299 stxa %g0, [tmp1]ASI_DC_TAG; /* flush line1 from dcache */ \
302 xor tmp1, tmp2, tmp1; \
303 stxa %g0, [tmp1]ASI_DC_TAG; /* flush line2 from dcache */ \
306 or tte, TTE_REF_INT, tmp1; \
307 casxa [ttepa]ASI_MEM, tte, tmp1; /* update ref bit */ \
308 cmp tte, tmp1; \
324 * tmp1 = tmp reg
330 #define TTE_SET_REFMOD_ML(tte, ttepa, tsbarea, tmp1, tmp2, label, \
340 GET_CPU_IMPL(tmp1); \
341 cmp tmp1, SPITFIRE_IMPL; \
343 cmp tmp1, CHEETAH_IMPL; \
346 lduh [tsbarea + TSBMISS_DMASK], tmp1; \
351 and ttepa, tmp1, tmp1; \
352 stxa %g0, [tmp1]ASI_DC_TAG; /* flush line1 from dcache */ \
355 xor tmp1, tmp2, tmp1; \
356 stxa %g0, [tmp1]ASI_DC_TAG; /* flush line2 from dcache */ \
359 or tte, TTE_HWWR_INT | TTE_REF_INT, tmp1; \
360 casxa [ttepa]ASI_MEM, tte, tmp1; /* update ref/mod bit */ \
361 cmp tte, tmp1; \
387 #define MAKE_TSBREG(tsbreg, tsbinfo, vabase, tmp1, tmp2, label) \
389 ldx [tsbinfo + TSBINFO_VADDR], tmp1; \
396 and tmp1, tsbreg, tsbreg; \
412 #define MAKE_TSBREG_SECTSB(tsbreg, tsb1, tsb2, tmp1, tmp2, tmp3, label) \
420 ldx [tsb1 + TSBINFO_VADDR], tmp1 ;\
422 and tmp1, tmp3, tmp1 ;\
425 or tmp1, tmp2, tmp3 ;\
427 lduh [tsb1 + TSBINFO_SZCODE], tmp1 ;\
429 and tmp1, TSB_SOFTSZ_MASK, tmp1 ;\
432 or tmp1, tmp2, tmp3 ;\
475 #define RESV_OFFSET(tsbinfo, resva, tmp1, label) \
477 lduh [tsbinfo + TSBINFO_SZCODE], tmp1 ;\
478 brgz,pn tmp1, label/**/9 ;\
480 ldx [tsbinfo + TSBINFO_VADDR], tmp1 ;\
483 sllx tmp1, (64 - MMU_PAGESHIFT4M), tmp1 ;\
484 srlx tmp1, (64 - MMU_PAGESHIFT4M), tmp1 ;\
485 or tmp1, resva, resva ;\
568 * tmp1, tmp2 = scratch registers
573 #define GET_2ND_TSBE_PTR(tagacc, tsbp8k, tsbe_ptr, tmp1, tmp2, label) \
576 GET_2ND_TSB_SIZE(tsbp8k, tmp1); \
577 /* tmp1 = TSB size code */ \
578 GET_TSBE_POINTER(MMU_PAGESHIFT4M, tsbe_ptr, tagacc, tmp1, tmp2)
600 #define GET_1ST_TSBE_PTR(tagacc, tsbe_ptr, tmp1, tmp2)
614 #define LOAD_TSBREG(tsbreg, tmp1, tmp2) \
615 mov MMU_TSB, tmp1; \
617 stxa tsbreg, [tmp1]ASI_DMMU; /* dtsb reg */ \
618 stxa tsbreg, [tmp1]ASI_IMMU; /* itsb reg */ \
717 #define SET_SHCTX_TAGACC(tmp1, tmp2, asi) \
723 mov MMU_SHARED_CONTEXT, tmp1 /* clobber tsbe_ptr */ ;\
724 ldxa [tmp1]ASI_MMU_CTX, tmp1 /* tmp2 = shctx reg */ ;\
725 sllx tmp1, SHCTXREG_CTX_LSHIFT, tmp1 ;\
726 srlx tmp1, SHCTXREG_CTX_LSHIFT, tmp1 /* tmp1 = SHCTX */ ;\
727 or tmp1, tmp2, tmp1 /* tmp1 = VA|SHCTX */ ;\
729 stxa tmp1, [tmp2]asi /* asi = VA|SHCTX */
783 #define SAVE_CTX1(traptype, tmp1, tmp2, label) \
788 SET_SHCTX_TAGACC(tmp1, tmp2, ASI_DMMU) ;\
792 SET_SHCTX_TAGACC(tmp1, tmp2, ASI_IMMU) ;\
793 sethi %hi(FLUSH_ADDR), tmp1 ;\
794 flush tmp1 ;\