Lines Matching refs:g2
789 mov t_flags, afar; /* depends on afar = %g2 */ \
1043 * temporarily save the values of %g1 and %g2.
1061 * We save the values of %g1 and %g2 in %tpc, %tnpc and %tstate (since
1063 * we need to put the low-order two bits of %g1 and %g2 in %tstate).
1066 * %g2 in bits 10-11 (insuring bits 8-9 are zero for use by the D$/I$
1075 wrpr %g2, %tnpc; \
1076 sllx %g2, CH_ERR_G2_TO_TSTATE_SHFT, %g2; \
1077 or %g1, %g2, %g2; \
1080 wrpr %g2, %tstate
1124 * structure and %g2 will have the original flags in the ch_err_tl1_data
1127 * All %g registers except for %g1, %g2 and %g5 will be available after
1131 * only %g1+%g2 (which we've saved in %tpc, %tnpc, %tstate)
1136 * original %g1+%g2 values (because we're going to change %tl).
1139 * 5. Reconstitute %g1+%g2 from %tpc (%g3), %tnpc (%g4),
1142 * 6. Load existing ch_err_tl1_data flags in %g2
1144 * 8. If %g2 is non-zero (the structure was busy), shift the new
1147 * 10. If %g2 is non-zero, read the %tpc and store it in
1151 GET_CH_ERR_TL1_PTR(%g1, %g2, CHPR_TL1_ERR_DATA); \
1172 ldxa [%g1 + CH_ERR_TL1_FLAGS]%asi, %g2; \
1174 brz %g2, 9f; \
1176 or %g2, %g4, %g3; \
1178 brnz %g2, 8f; \
1194 andn %g1, DCU_DC + DCU_IC, %g2; \
1195 stxa %g2, [%g0]ASI_DCU; \
1197 rdpr %tstate, %g2; \
1200 or %g1, %g2, %g2; \
1201 wrpr %g2, %tstate; \
1220 CPU_INDEX(%g2, %g3); \
1223 stb %g4, [%g2 + %g3]; \
1224 mov 1, %g2; \
1225 sll %g2, PIL_15, %g2; \
1226 wr %g2, SET_SOFTINT; \
1232 ldxa [%g1 + CH_ERR_TL1_G2]%asi, %g2; \
1239 * 1. Sets flags in ch_err_tl1_data and leaves in %g2 (first
1244 label: ldxa [%g1 + CH_ERR_TL1_FLAGS]%asi, %g2; \
1245 or %g2, CH_ERR_TL | CH_ERR_PANIC, %g2; \
1246 stxa %g2, [%g1 + CH_ERR_TL1_FLAGS]%asi; \