Lines Matching refs:bus
88 #define UPDATE_CIC_HISTORY(reg, brd, bus, val) \
90 BOARDSET_ADD(xf_cicbuses, (bus)), \
91 xf_cicregs[brd][bus][reg] = (val))
124 #define UPDATE_CIC_HISTORY(reg, brd, bus, val)
154 static int cic_write_sm_mask(int board, int bus, boardset_t sm_mask);
155 static int cic_write_sm_bar(int board, int bus, uint_t sm_bar);
156 static int cic_write_sm_lar(int board, int bus, uint_t sm_lar);
161 static int verify_smregs(int brd, int bus, boardset_t smmask,
185 cic_read_domain_mask(int board, int bus)
194 bus);
196 proc, board, bus, csr_addr);
204 cic_read_sm_mask(int board, int bus)
213 bus);
215 proc, board, bus, csr_addr);
223 cic_write_sm_mask(int board, int bus, boardset_t sm_mask)
243 bus);
245 proc, board, bus, csr_addr);
249 UPDATE_CIC_HISTORY(CICREG_SMMASK, board, bus, sm_mask);
262 cic_read_sm_bar(int board, int bus)
271 bus);
273 proc, board, bus, csr_addr);
279 bus);
281 proc, board, bus, csr_addr);
289 cic_write_sm_bar(int board, int bus, uint_t sm_bar)
309 bus);
311 proc, board, bus, csr_addr);
315 UPDATE_CIC_HISTORY(CICREG_SMBAR, board, bus, sm_bar);
336 bus);
338 proc, board, bus, csr_addr);
358 cic_read_sm_lar(int board, int bus)
367 bus);
369 proc, board, bus, csr_addr);
375 bus);
377 proc, board, bus, csr_addr);
385 cic_write_sm_lar(int board, int bus, uint_t sm_lar)
405 bus);
407 proc, board, bus, csr_addr);
411 UPDATE_CIC_HISTORY(CICREG_SMLAR, board, bus, sm_lar);
432 bus);
434 proc, board, bus, csr_addr);
944 * There will always be a bus 0 (logical).
1041 int rv, cpuid, brd, bus;
1062 for (bus = 0; bus < MAX_ABUSES; bus++) {
1066 if (!(idnxfp->xf_abus_mask & (1 << bus)))
1068 smmask = cic_read_sm_mask(brd, bus);
1072 (void) cic_write_sm_mask(brd, bus, smmask);
1075 (void) cic_write_sm_bar(brd, bus,
1077 (void) cic_write_sm_lar(brd, bus,
1083 rv = verify_smregs(brd, bus, smmask, idnxfp->xf_smbase,
1087 (void) cic_write_sm_mask(brd, bus, smmask);
1098 (void) cic_write_sm_lar(brd, bus, 0);
1099 (void) cic_write_sm_bar(brd, bus, 1);
1101 rv = verify_smregs(brd, bus, smmask, 1, 0);
1103 rv = verify_smregs(brd, bus, smmask,
1108 idnxf_cic_info.xf_errcic[brd][bus] = IDNCIC_ERR;
1111 idnxf_cic_info.xf_errcic[brd][bus] = IDNCIC_OK;
1126 int c, brd, bus;
1253 for (bus = 0; bus < MAX_ABUSES; bus++) {
1255 if (!(abus_mask & (1 << bus)))
1258 switch (idnxf_cic_info.xf_errcic[brd][bus]) {
1276 brd, bus, smbase, smlimit);
1291 PR_REGS("%s: board %d, bus %d "
1293 proc, brd, bus, smbase, smlimit);
1346 * bus config information.
1455 * bus config information.
1589 verify_smregs(int brd, int bus, boardset_t smmask, uint_t smbase, uint_t
1596 smreg = (uint_t)cic_read_sm_mask(brd, bus);
1607 smreg = cic_read_sm_bar(brd, bus);
1618 smreg = cic_read_sm_lar(brd, bus);