Lines Matching refs:be
157 ! to be zero, the following casxa instruction must specify
159 ! This ASI must be specified explicitly (via casxa), rather
206 ! will fail the idle check. This could be made more lenient
209 ! Assumed to be 0x18 for local ASI access or else
214 ! asi: Immediate asi value. Assumed to be ASI_SAFARI_CONFIG
246 ! is ready to be removed from domain coherency.
318 be %xcc, drmach_shutdown_ecache_flushed
323 ! sync, all writes must be strictly managed.
359 ! will be of the remote flavor.
410 ! Global drmach_xt_mb[cpuid] is expected to be the new LPA.
436 ! to be a VA which is polled via ASI_SAFARI_CONFIG until the
438 ! must be returned along with an error code if the MCU status
440 ! This section will be empty if this processor is not a Panther.
441 ! Both the address and id are assumed to be 64 bit values.
444 ! address is assumed to be a PIO address which is polled via
446 ! id is an opaque identifier which must be returned along with
450 ! assumed to be 64 bit values.
453 ! assumed to be a VA within ASM_MC_DECODE space. The
457 ! be 64 bit values.
462 ! via ASI_IO. The address element is assumed to be a 64 bit
463 ! value. The value element is assumed to be a 64 bit word
484 be,a 3b ! ok, advance
498 be,a 4b ! ok, advance
578 ! The special interrupt vector is assumed to be a cross-call to
702 ! will disturb the E$. The lines of the bus sync list will be
703 ! in state S. The line containing drmach_xt_ready will be in
707 ! However, the lines containing the bus sync list must be
710 ! memory will be in state gM. The resulting S,gM state pair is
712 ! E$ after the bus sync list is read will be sufficient to
717 ! flush of the shared caches, however care must be taken that the
770 be 3f
887 ! %o0 = base vaddr of area to clear (must be 64-byte aligned)
888 ! %o1 = size of area to clear (must be multiple of 256 bytes)