Lines Matching defs:reg
174 * Safari Config reg (7 secs).
2954 * For Panther MCs, append the MC idle reg address and drmach_mem_t pointer.
3001 /* addr/id tuple for local Panther MC idle reg */
3065 * Step 2: Now rewrite target reg with present bit on.
3170 DRMACH_PR("local Panther MC idle reg (via ASI 0x4a):\n");
3179 DRMACH_PR("non-local Panther MC idle reg (via ASI 0x15):\n");
3790 rv = node->n_getproplen(node, "reg", &len);
3797 (uint_t)node->get_dnode(node), "reg");
3801 rv = node->n_getprop(node, "reg", (void *)regs, sizeof (regs));
3807 (uint_t)node->get_dnode(node), "reg");
5143 drmach_reg_t reg;
5149 * it represents a CMP device. For a CMP, the reg
5161 if (np->n_getproplen(np, "reg", &len) != 0)
5164 if (len != sizeof (reg))
5167 if (np->n_getprop(np, "reg", ®, sizeof (reg)) != 0)
5171 *p = ((uint64_t)reg.reg_addr_hi << 32) | reg.reg_addr_lo;
5725 DDI_PROP_DONTPASS, "reg", (caddr_t)®buf,
5784 "reg", (caddr_t)®buf, &len) == DDI_PROP_SUCCESS) {
6241 * addressed registers. The reg property's hi and lo fields
7859 drmach_is_slot1_pause_axq(dev_info_t *dip, char *name, int *id, uint64_t *reg)
7889 "reg", (caddr_t)regs, ®len) != DDI_PROP_SUCCESS) {
7890 DRMACH_PR("drmach_is_slot1_pause_axq: no reg prop for "
7895 ASSERT(id && reg);
7896 *reg = (uint64_t)regs[0].reg_addr_hi << 32;
7897 *reg |= (uint64_t)regs[0].reg_addr_lo;
7908 uint64_t reg, drmach_slot1_pause_t **slot1_paused)
7936 slot1->axq.reg_basepa = reg;
8002 "reg", (caddr_t)regs, ®len) != DDI_PROP_SUCCESS) {
8003 DRMACH_PR("drmach_find_slot1_io: no reg prop for pci "
8067 uint64_t reg;
8083 reg = pci->regs[iter].slot_intr_state_diag;
8084 while (reg) {
8092 if ((reg & COMMON_CLEAR_INTR_REG_MASK) !=
8098 ino * sizeof (reg));
8103 reg >>= 2;
8119 reg = pci->regs[iter].obio_intr_state_diag;
8120 while (reg && ino <= 0x38) {
8121 if ((reg & COMMON_CLEAR_INTR_REG_MASK) !=
8127 ino * sizeof (reg));
8132 reg >>= 2;
8138 kmem_zalloc(cnt * sizeof (reg), KM_SLEEP);
8146 uint32_t reg;
8156 * input to bits 0-6 of perf cntr select reg.
8158 reg = axq->pcr_sel_save;
8159 reg &= ~AXQ_PIC_CLEAR_MASK;
8160 reg |= L2_IO_Q;
8162 stphysio(axq->reg_basepa + AXQ_SLOT1_PERFCNT_SEL, reg);
8311 * error in the error ctrl reg.
8317 uint64_t reg;
8332 reg = pci->regs[iter].intr_map_regs[n];
8333 if (reg & COMMON_INTR_MAP_REG_VALID) {
8334 ino = reg & COMMON_INTR_MAP_REG_INO;
8368 exp, unum, (i == 0) ? 'A' : 'B', ino, reg);
8540 uint64_t reg;
8550 drmach_is_slot1_pause_axq(dip, name, &portid, ®)) {
8551 drmach_slot1_pause_add_axq(dip, name, portid, reg,