Lines Matching refs:CPU
28 * CPU management for serengeti DR
30 * There are three states a CPU can be in:
56 * SIR (Software Initiated Reset) is used to unconfigure a CPU.
57 * After the CPU has completed flushing the caches, it issues an
60 * completes successfully, the CPU will be idling in OBP.
131 * registers on the CPU when it is being put into reset.
139 * Mark the CPU in reset. This should be done before calling
146 * Ask OBP to mark the CPU as in POST
155 * Ask the SC to put the CPU into reset. If the first
156 * core is not present, the stop CPU interface needs
210 * Ask the SC to bring the CPU out of reset.
211 * At this point, the sb_dev_present bit is not set for the CPU.
212 * From sbd point of view the CPU is not present yet. No
213 * status threads will try to read registers off the CPU.
230 * If the first core is not present, the start CPU
254 * Mark the CPU out of reset.
303 * This is a safe guard in case the CPU has taken a trap
403 cmn_err(CE_WARN, "cpu%d: Key \"%s\" missing from CPU SRAM TOC",
409 cmn_err(CE_WARN, "cpu%d: CPU SRAM key \"%s\" not page aligned, "
416 cmn_err(CE_WARN, "cpu%d: CPU SRAM key \"%s\" too small, "
426 * The CPU's remain paused and the prom_mutex is known to be free.
434 * Quiesce interrupts on the target CPU. We do this by setting
435 * the CPU 'not ready'- (i.e. removing the CPU from cpu_ready_set) to
448 * routine to make the CPU go through POST and re-enter OBP.
460 * CPU to reach OBP idle loop.
469 cmn_err(CE_WARN, "cpu%d: CPU failed to enter OBP idle loop.\n",
612 * A detaching CPU is xcalled with an xtrap to sbdp_cpu_stop_self() after
616 * elsewhere) and that the CPU not reference anything on any other board
622 * 1) Create a locked mapping to a location in CPU SRAM where
625 * the cpu will execute into CPU SRAM.
626 * 3) Jump into function with CPU SRAM.
639 cpu_t *cp = CPU;
790 cpu_t *cp = CPU;
813 cmn_err(CE_PANIC, "sbdp_cpu_shutdown_self: CPU %d FAILED TO SHUTDOWN",