Lines Matching refs:g5
550 add %sp, 32, %g5 ;\
551 stxa %l4, [%g5 + %g1]asi_num ;\
552 stxa %l5, [%g5 + %g2]asi_num ;\
553 stxa %l6, [%g5 + %g3]asi_num ;\
554 stxa %l7, [%g5 + %g4]asi_num ;\
555 add %g5, 32, %g5 ;\
556 stxa %i0, [%g5 + %g1]asi_num ;\
557 stxa %i1, [%g5 + %g2]asi_num ;\
558 stxa %i2, [%g5 + %g3]asi_num ;\
559 stxa %i3, [%g5 + %g4]asi_num ;\
560 add %g5, 32, %g5 ;\
561 stxa %i4, [%g5 + %g1]asi_num ;\
562 stxa %i5, [%g5 + %g2]asi_num ;\
563 stxa %i6, [%g5 + %g3]asi_num ;\
564 stxa %i7, [%g5 + %g4]asi_num ;\
650 add %sp, 32, %g5 ;\
651 ldxa [%g5 + %g1]asi_num, %l4 ;\
652 ldxa [%g5 + %g2]asi_num, %l5 ;\
653 ldxa [%g5 + %g3]asi_num, %l6 ;\
654 ldxa [%g5 + %g4]asi_num, %l7 ;\
655 add %g5, 32, %g5 ;\
656 ldxa [%g5 + %g1]asi_num, %i0 ;\
657 ldxa [%g5 + %g2]asi_num, %i1 ;\
658 ldxa [%g5 + %g3]asi_num, %i2 ;\
659 ldxa [%g5 + %g4]asi_num, %i3 ;\
660 add %g5, 32, %g5 ;\
661 ldxa [%g5 + %g1]asi_num, %i4 ;\
662 ldxa [%g5 + %g2]asi_num, %i5 ;\
663 ldxa [%g5 + %g3]asi_num, %i6 ;\
664 ldxa [%g5 + %g4]asi_num, %i7 ;\
801 add %sp, 32, %g5 ;\
802 stxa %l4, [%g5 + %g1]asi_num ;\
803 stxa %l5, [%g5 + %g2]asi_num ;\
804 stxa %l6, [%g5 + %g3]asi_num ;\
805 stxa %l7, [%g5 + %g4]asi_num ;\
806 add %g5, 32, %g5 ;\
807 stxa %i0, [%g5 + %g1]asi_num ;\
808 stxa %i1, [%g5 + %g2]asi_num ;\
809 stxa %i2, [%g5 + %g3]asi_num ;\
810 stxa %i3, [%g5 + %g4]asi_num ;\
811 add %g5, 32, %g5 ;\
812 stxa %i4, [%g5 + %g1]asi_num ;\
813 stxa %i5, [%g5 + %g2]asi_num ;\
814 stxa %i6, [%g5 + %g3]asi_num ;\
815 stxa %i7, [%g5 + %g4]asi_num ;\
862 mov ttype, %g5 ;\
959 rdpr %pstate, %g5 ;\
960 wrpr %g5, PSTATE_MG | PSTATE_AG, %pstate
1031 mov MMU_PCONTEXT, %g5 ;\
1036 ldxa [%g5]ASI_DMMU, %g6 /* g6 = primary ctx */ ;\
1041 mov MMU_SCONTEXT, %g5 ;\
1042 ldxa [%g5]ASI_DMMU, %g6 /* g6 = secondary ctx */ ;\
1085 ldda [%g1]ASI_QUAD_LDD_PHYS, %g4 /* g4 = tag, %g5 data */;\
1090 stxa %g5, [%g0]ASI_DTLB_IN /* trapstat expects TTE */ ;\
1091 retry /* in %g5 */ ;\
1122 ldda [%g1]ASI_NQUAD_LD, %g4 /* g4 = tag, %g5 data */ ;\
1127 stxa %g5, [%g0]ASI_DTLB_IN /* trapstat expects TTE */ ;\
1128 retry /* in %g5 */ ;\
1176 ldda [%g1]ASI_QUAD_LDD_PHYS, %g4 /* g4 = tag, g5 = data */ ;\
1179 andcc %g5, TTE_EXECPRM_INT, %g0 /* check execute bit */ ;\
1183 stxa %g5, [%g0]ASI_ITLB_IN /* trapstat expects %g5 */ ;\
1215 ldda [%g1]ASI_NQUAD_LD, %g4 /* g4 = tag, g5 = data */ ;\
1219 andcc %g5, TTE_EXECPRM_INT, %g0 /* check execute bit */ ;\
1223 stxa %g5, [%g0]ASI_ITLB_IN /* trapstat expects %g5 */ ;\
1285 * g5 = tsbe data (in)
1299 stxa %g5, [%g3 + TRAP_ENT_F1]%asi /* tsb data */ ;\
1597 * g5 = tsbe data (in)
1618 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps?
1619 brz,pt %g5, 2f
1621 ldn [%g5 + P_UTRAP15], %g5 ! unaligned utrap?
1622 brz,pn %g5, 2f
1644 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps?
1645 brz,pt %g5, 1f
1647 ldn [%g5 + P_UTRAP16], %g5
1648 brnz,pt %g5, .setup_v9utrap
1654 CPU_INDEX(%g4, %g5)
1655 set cpu_core, %g5
1657 add %g4, %g5, %g4
1658 lduh [%g4 + CPUC_DTRACE_FLAGS], %g5
1659 andcc %g5, CPU_DTRACE_NOFAULT, %g0
1661 or %g5, CPU_DTRACE_BADADDR, %g5
1662 stuh %g5, [%g4 + CPUC_DTRACE_FLAGS]
1666 GET_CPU_IMPL(%g5) ! check SFSR.FT to see if this
1667 cmp %g5, PANTHER_IMPL ! is a TLB parity error. But
1712 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps?
1713 brz,a,pt %g5, 2f
1715 ldn [%g5 + P_UTRAP7], %g5 ! fp_disabled utrap?
1716 brz,a,pn %g5, 2f
1741 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps?
1742 brz,a,pt %g5, 1f
1744 ldn [%g5 + P_UTRAP8], %g5
1745 brnz,a,pt %g5, .setup_v9utrap
1754 * %g5 user trap handler
1788 wrpr %g0, %g5, %tnpc ! trap handler address
1798 ldn [%g4 + CPU_THREAD], %g5 ! load thread pointer
1799 ldn [%g5 + T_PROCP], %g5 ! load proc pointer
1800 ldn [%g5 + P_UTRAPS], %g5 ! are there utraps?
1806 brz,pt %g5, 3f ! if p_utraps == NULL goto trap()
1813 brz,a,pt %g5, 3f ! if p_utraps == NULL goto trap()
1831 ldn [%g5 + %g2], %g5
1832 brnz,a,pt %g5, .setup_v9utrap
1842 * %g5 user trap handler
1885 stn %g5, [%g1 + PCB_TRACEPC] ! save trap handler addr in pcb
1894 wrpr %g0, %g5, %tnpc ! trap handler address
1937 set FSR_TEM_NX, %g5
1939 andcc %g2, %g5, %g0
1941 rdpr %tpc, %g5 ! get faulting PC
1945 lda [%g5]ASI_USER, %g6 ! get user's instruction
1950 set FITOS_INSTR, %g5
1951 cmp %g7, %g5
2069 ldx [%g7], %g5
2071 add %g5, 1, %g6
2073 casxa [%g7] ASI_N, %g5, %g6
2074 cmp %g5, %g6
2076 or %g0, %g6, %g5
2082 ldx [%g7], %g5
2084 add %g5, 1, %g6
2086 casxa [%g7] ASI_N, %g5, %g6
2087 cmp %g5, %g6
2089 or %g0, %g6, %g5
2115 CPU_ADDR(%g4, %g5)
2119 ld [%g4 + MPCB_WSTATE], %g5
2120 add %g5, WSTATE_CLEAN_OFFSET, %g5
2121 wrpr %g0, %g5, %wstate
2131 sethi %hi(nwin_minus_one), %g5
2132 ld [%g5 + %lo(nwin_minus_one)], %g5 ! %g5 = nwin - 1
2135 movneg %xcc, %g5, %g6 ! if (%g6<0) %g6 = nwin-1
2304 ldxa [MMU_SFAR]%asi, %g5 ! misaligned vaddr in %g5
2343 lduwa [%g5]ASI_USER, %g7 ! get first half of misaligned data
2344 add %g5, 4, %g5 ! increment misaligned data address
2345 lduwa [%g5]ASI_USER, %g5 ! get second half of misaligned data
2348 or %g5, %g7, %g5 ! combine data
2350 stx %g5, [%g7 + CPU_TMP1] ! save in cpu_tmp1
2365 mov %g5, %g2 ! misaligned vaddr in %g2
2374 ldxa [MMU_SFAR]%asi, %g5 ! misaligned vaddr in %g5
2415 stuwa %g7, [%g5]ASI_USER ! first half
2416 add %g5, 4, %g5 ! increment misaligned data address
2417 stuwa %g6, [%g5]ASI_USER ! second half
2428 mov %g5, %g2 ! misaligned vaddr in %g2
2636 TRACE_PTR(%g5, %g6)
2638 stxa %g6, [%g5 + TRAP_ENT_TICK]%asi
2640 stha %g6, [%g5 + TRAP_ENT_TL]%asi
2642 stha %g6, [%g5 + TRAP_ENT_TT]%asi
2644 stxa %g6, [%g5 + TRAP_ENT_TSTATE]%asi
2645 stna %sp, [%g5 + TRAP_ENT_SP]%asi
2646 stna %g0, [%g5 + TRAP_ENT_TR]%asi
2648 stna %g6, [%g5 + TRAP_ENT_TPC]%asi
2651 stxa %g6, [%g5 + TRAP_ENT_F1]%asi
2655 stxa %g6, [%g5 + TRAP_ENT_F2]%asi
2657 stna %g6, [%g5 + TRAP_ENT_F3]%asi
2658 stna %g6, [%g5 + TRAP_ENT_F4]%asi
2659 TRACE_NEXT(%g5, %g6, %g7)
2662 GET_CPU_IMPL(%g5)
2663 cmp %g5, PANTHER_IMPL
2666 rdpr %tt, %g5
2667 cmp %g5, T_DATA_EXCEPTION
2671 ldxa [MMU_SFSR]%asi, %g5
2674 andcc %g5, %g6, %g0
2681 mov %g5, %g3
2698 CPU_ADDR(%g6, %g5)
2700 GET_CPU_IMPL(%g5)
2701 cmp %g5, CHEETAH_IMPL
2703 cmp %g5, SPITFIRE_IMPL
2710 sethi %hi(dcache_line_mask), %g5
2711 ld [%g5 + %lo(dcache_line_mask)], %g5
2712 and %g6, %g5, %g5
2713 stxa %g0, [%g5]ASI_DC_TAG
2720 rdpr %tt, %g5
2740 cmp %g5, T_ALIGNMENT
2832 TRACE_NEXT(%g3, %g4, %g5)
2849 * g5 = tsbe data (in)
2854 ! Do not disturb %g5, it will be used after the trace
2867 * g5 - g6 = scratch (clobbered)
2875 TRACE_PTR(%g5, %g6)
2876 stxa %g2, [%g5 + TRAP_ENT_SP]%asi ! tag access
2877 stxa %g4, [%g5 + TRAP_ENT_F1]%asi ! tsb tag
2879 stxa %g6, [%g5 + TRAP_ENT_TICK]%asi
2881 stxa %g6, [%g5 + TRAP_ENT_F2]%asi
2882 stna %g1, [%g5 + TRAP_ENT_F3]%asi ! tsb8k pointer
2884 stna %g6, [%g5 + TRAP_ENT_F4]%asi ! huh?
2886 stna %g6, [%g5 + TRAP_ENT_TPC]%asi
2888 stha %g6, [%g5 + TRAP_ENT_TL]%asi
2891 stha %g4, [%g5 + TRAP_ENT_TT]%asi
2896 1: stxa %g6, [%g5 + TRAP_ENT_TSTATE]%asi ! tag target
2897 stxa %g3, [%g5 + TRAP_ENT_TR]%asi ! tsb4m pointer
2898 TRACE_NEXT(%g5, %g4, %g6)
2911 GET_TRACE_TICK(%g6, %g5)
2927 TRACE_NEXT(%g1, %g4, %g5)
2982 rdpr %tpc, %g5
2984 andncc %g5, %g6, %g0 ! check lower 14 bits of %tpc
2986 ldxa [%g0]ASI_INTR_RECEIVE_STATUS, %g5
2991 ldxa [%g0]ASI_INTR_RECEIVE_STATUS, %g5
2994 and %g5, IRSR_BUSY, %g5
2995 orcc %g5, %g6, %g0
3006 rdpr %tnpc, %g5
3007 wrpr %g0, %g5, %tpc
3008 add %g5, 4, %g5
3009 wrpr %g0, %g5, %tnpc