Lines Matching refs:g4
83 * %g4 desire %pil
128 sub %g0, 1, %g4 ;\
160 sub %g0, 1, %g4 ;\
179 sub %g0, 1, %g4 ;\
201 sub %g0, 1, %g4 ;\
241 sub %g0, 1, %g4 ;\
252 sub %g0, 1, %g4 ;\
259 sub %g0, 1, %g4 ;\
345 add %sp, 16, %g4 ;\
346 sta %l4, [%g4 + %g0]asi_num ;\
347 sta %l5, [%g4 + %g1]asi_num ;\
348 sta %l6, [%g4 + %g2]asi_num ;\
349 sta %l7, [%g4 + %g3]asi_num ;\
350 add %g4, 16, %g4 ;\
351 sta %i0, [%g4 + %g0]asi_num ;\
352 sta %i1, [%g4 + %g1]asi_num ;\
353 sta %i2, [%g4 + %g2]asi_num ;\
354 sta %i3, [%g4 + %g3]asi_num ;\
355 add %g4, 16, %g4 ;\
356 sta %i4, [%g4 + %g0]asi_num ;\
357 sta %i5, [%g4 + %g1]asi_num ;\
358 sta %i6, [%g4 + %g2]asi_num ;\
359 sta %i7, [%g4 + %g3]asi_num ;\
450 add %sp, 16, %g4 ;\
451 lda [%g4 + %g0]asi_num, %l4 ;\
452 lda [%g4 + %g1]asi_num, %l5 ;\
453 lda [%g4 + %g2]asi_num, %l6 ;\
454 lda [%g4 + %g3]asi_num, %l7 ;\
455 add %g4, 16, %g4 ;\
456 lda [%g4 + %g0]asi_num, %i0 ;\
457 lda [%g4 + %g1]asi_num, %i1 ;\
458 lda [%g4 + %g2]asi_num, %i2 ;\
459 lda [%g4 + %g3]asi_num, %i3 ;\
460 add %g4, 16, %g4 ;\
461 lda [%g4 + %g0]asi_num, %i4 ;\
462 lda [%g4 + %g1]asi_num, %i5 ;\
463 lda [%g4 + %g2]asi_num, %i6 ;\
464 lda [%g4 + %g3]asi_num, %i7 ;\
548 mov 24 + V9BIAS64, %g4 ;\
549 stxa %l3, [%sp + %g4]asi_num ;\
554 stxa %l7, [%g5 + %g4]asi_num ;\
559 stxa %i3, [%g5 + %g4]asi_num ;\
564 stxa %i7, [%g5 + %g4]asi_num ;\
648 mov V9BIAS64 + 24, %g4 ;\
649 ldxa [%sp + %g4]asi_num, %l3 ;\
654 ldxa [%g5 + %g4]asi_num, %l7 ;\
659 ldxa [%g5 + %g4]asi_num, %i3 ;\
664 ldxa [%g5 + %g4]asi_num, %i7 ;\
770 add %sp, 16, %g4 ;\
771 sta %l4, [%g4 + %g0]asi_num ;\
772 sta %l5, [%g4 + %g1]asi_num ;\
773 sta %l6, [%g4 + %g2]asi_num ;\
774 sta %l7, [%g4 + %g3]asi_num ;\
775 add %g4, 16, %g4 ;\
776 sta %i0, [%g4 + %g0]asi_num ;\
777 sta %i1, [%g4 + %g1]asi_num ;\
778 sta %i2, [%g4 + %g2]asi_num ;\
779 sta %i3, [%g4 + %g3]asi_num ;\
780 add %g4, 16, %g4 ;\
781 sta %i4, [%g4 + %g0]asi_num ;\
782 sta %i5, [%g4 + %g1]asi_num ;\
783 sta %i6, [%g4 + %g2]asi_num ;\
784 sta %i7, [%g4 + %g3]asi_num ;\
799 mov 24 + V9BIAS64, %g4 ;\
800 stxa %l3, [%sp + %g4]asi_num ;\
805 stxa %l7, [%g5 + %g4]asi_num ;\
810 stxa %i3, [%g5 + %g4]asi_num ;\
815 stxa %i7, [%g5 + %g4]asi_num ;\
884 sethi %hi(.check_v9utrap), %g4 ;\
885 jmp %g4 + %lo(.check_v9utrap) ;\
896 sethi %hi(.check_v9utrap), %g4 ;\
897 jmp %g4 + %lo(.check_v9utrap) ;\
908 sethi %hi(.check_v9utrap), %g4 ;\
909 jmp %g4 + %lo(.check_v9utrap) ;\
919 sethi %hi(.check_v9utrap), %g4 ;\
920 jmp %g4 + %lo(.check_v9utrap) ;\
933 mov level, %g4 ;\
938 mov PIL_14, %g4 ;\
943 mov PIL_15, %g4 ;\
1033 sethi %hi(TAGACC_CTX_MASK), %g4 ;\
1034 or %g4, %lo(TAGACC_CTX_MASK), %g4 ;\
1035 and %g2, %g4, %g3 /* g3 = ctx */ ;\
1037 and %g6, %g4, %g6 /* &= CTXREG_CTX_MASK */ ;\
1040 andn %g2, %g4, %g1 /* ctx = primary */ ;\
1043 and %g6, %g4, %g6 /* &= CTXREG_CTX_MASK */ ;\
1085 ldda [%g1]ASI_QUAD_LDD_PHYS, %g4 /* g4 = tag, %g5 data */;\
1086 cmp %g4, %g7 ;\
1122 ldda [%g1]ASI_NQUAD_LD, %g4 /* g4 = tag, %g5 data */ ;\
1123 cmp %g4, %g7 ;\
1176 ldda [%g1]ASI_QUAD_LDD_PHYS, %g4 /* g4 = tag, g5 = data */ ;\
1177 cmp %g4, %g7 ;\
1215 ldda [%g1]ASI_NQUAD_LD, %g4 /* g4 = tag, g5 = data */ ;\
1216 cmp %g4, %g7 ;\
1253 * g4 = ???? ;\
1284 * g3 - g4 = scratch (clobbered)
1296 GET_TRACE_TICK(%g6, %g4) ;\
1312 ldxa [%g0]ASI_DMMU, %g4 ;\
1314 movne %icc, %g4, %g1 ;\
1317 TRACE_NEXT(%g3, %g4, %g6)
1596 * g3 - g4 = scratch (clobbered)
1603 mov MMU_TAG_ACCESS, %g4
1604 ldxa [%g4]ASI_IMMU, %g2 ! arg1 = addr
1608 mov -1, %g4
1615 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1641 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1654 CPU_INDEX(%g4, %g5)
1656 sllx %g4, CPU_CORE_SHIFT, %g4
1657 add %g4, %g5, %g4
1658 lduh [%g4 + CPUC_DTRACE_FLAGS], %g5
1662 stuh %g5, [%g4 + CPUC_DTRACE_FLAGS]
1669 mov 1, %g4 ! running on Panther CPUs
1670 sllx %g4, PN_SFSR_PARITY_SHIFT, %g4 ! since US-I/II use the same
1671 andcc %g3, %g4, %g0 ! bit for something else which
1677 set itlb_parity_trap, %g4
1681 set dtlb_parity_trap, %g4
1690 sub %g0, 1, %g4
1692 jmp %g4 ! off to the appropriate
1696 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1702 rdpr %tstate, %g4
1703 btst TSTATE_PRIV, %g4
1729 sub %g0, 1, %g4
1736 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1750 sub %g0, 1, %g4
1760 sub %g0, 1, %g4 ! the save instruction below
1769 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1785 rdpr %cwp, %g4
1787 wrpr %g1, %g4, %tstate
1797 CPU_ADDR(%g4, %g1) ! load CPU struct addr
1798 ldn [%g4 + CPU_THREAD], %g5 ! load thread pointer
1821 st %g1, [%g4 + CPU_TL1_HDLR] ! set CPU_TL1_HDLR
1824 st %g0, [%g4 + CPU_TL1_HDLR] ! clr CPU_TL1_HDLR
1826 sethi %hi(0xc1c00000), %g4 ! setup mask for illtrap instruction
1827 andcc %g1, %g4, %g4 ! and instruction with mask
1828 bnz,a,pt %icc, 3f ! if %g4 == zero, %g1 is an ILLTRAP
1837 sub %g0, 1, %g4
1847 sub %g0, 1, %g4 ! the save instruction below
1856 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1870 rdpr %cwp, %g4
1872 wrpr %g2, %g4, %tstate
1874 ldn [%g1 + T_PROCP], %g4 ! load proc pointer
1875 ldn [%g4 + P_AS], %g4 ! load as pointer
1876 ldn [%g4 + A_USERLIMIT], %g4 ! load as userlimit
1877 cmp %l7, %g4 ! check for single-step set
1881 ld [%g1 + PCB_STEP], %g4 ! load single-step flag
1882 cmp %g4, STEP_ACTIVE ! step flags set in pcb?
1886 mov %l7, %g4 ! on entry to precise user trap
1889 wrpr %g0, %g4, %tnpc ! generate FLTBOUNDS,
1890 ! %g4 == userlimit
1899 CPU_ADDR(%g1, %g4)
1975 set _fitos_fitod_table, %g4
1977 jmp %g4 + %g7
2021 set _fitos_fdtos_table, %g4
2023 jmp %g4 + %g7
2102 sub %g0, 1, %g4
2109 sub %g0, 1, %g4
2115 CPU_ADDR(%g4, %g5)
2116 ldn [%g4 + CPU_MPCB], %g4
2117 brz,a,pn %g4, 1f
2119 ld [%g4 + MPCB_WSTATE], %g5
2312 CPU_ADDR(%g1, %g4)
2313 or %g0, 1, %g4
2314 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag
2354 LDDF_REG(%g3, %g7, %g4)
2356 CPU_ADDR(%g1, %g4)
2360 CPU_ADDR(%g1, %g4)
2368 sub %g0, 1, %g4
2382 CPU_ADDR(%g1, %g4)
2383 or %g0, 1, %g4
2384 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag
2411 STDF_REG(%g6, %g7, %g4) ! STDF_REG(REG, ADDR, TMP)
2419 CPU_ADDR(%g1, %g4)
2423 CPU_ADDR(%g1, %g4)
2431 sub %g0, 1, %g4
2436 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4
2438 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0
2447 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4
2449 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0
2536 srlx %g2, PSR_FPRS_FEF_SHIFT, %g4 ! shift ef to V9 fprs.fef
2537 wr %g0, %g4, %fprs ! write fprs
2543 stuw %g4, [%g2 + FPU_FPRS] ! write fef value to fpu_fprs
2544 srlx %g4, 2, %g4 ! shift fef value to bit 0
2545 stub %g4, [%g2 + FPU_EN] ! write fef value to fpu_en
2792 set CTXREG_CTX_MASK, %g4 ! check Pcontext
2793 btst %g4, %g1
2821 GET_TRACE_TICK(%g6, %g4)
2832 TRACE_NEXT(%g3, %g4, %g5)
2848 * g3 - g4 = scratch (clobbered)
2866 * g4 = tsbe tag (in/clobbered)
2877 stxa %g4, [%g5 + TRAP_ENT_F1]%asi ! tsb tag
2878 GET_TRACE_TICK(%g6, %g4)
2890 or %g6, TT_MMU_MISS, %g4
2891 stha %g4, [%g5 + TRAP_ENT_TT]%asi
2898 TRACE_NEXT(%g5, %g4, %g6)
2927 TRACE_NEXT(%g1, %g4, %g5)
3016 mov -1, %g4