Lines Matching refs:g2
82 * %g2, %g3 args for above
341 mov 8, %g2 ;\
342 sta %l2, [%sp + %g2]asi_num ;\
348 sta %l6, [%g4 + %g2]asi_num ;\
353 sta %i2, [%g4 + %g2]asi_num ;\
358 sta %i6, [%g4 + %g2]asi_num ;\
445 mov 8, %g2 ;\
448 lda [%sp + %g2]asi_num, %l2 ;\
453 lda [%g4 + %g2]asi_num, %l6 ;\
458 lda [%g4 + %g2]asi_num, %i2 ;\
463 lda [%g4 + %g2]asi_num, %i6 ;\
544 mov 8 + V9BIAS64, %g2 ;\
545 stxa %l1, [%sp + %g2]asi_num ;\
552 stxa %l5, [%g5 + %g2]asi_num ;\
557 stxa %i1, [%g5 + %g2]asi_num ;\
562 stxa %i5, [%g5 + %g2]asi_num ;\
644 mov V9BIAS64 + 8, %g2 ;\
645 ldxa [%sp + %g2]asi_num, %l1 ;\
652 ldxa [%g5 + %g2]asi_num, %l5 ;\
657 ldxa [%g5 + %g2]asi_num, %i1 ;\
662 ldxa [%g5 + %g2]asi_num, %i5 ;\
766 mov 8, %g2 ;\
767 sta %l2, [%sp + %g2]asi_num ;\
773 sta %l6, [%g4 + %g2]asi_num ;\
778 sta %i2, [%g4 + %g2]asi_num ;\
783 sta %i6, [%g4 + %g2]asi_num ;\
795 mov 8 + V9BIAS64, %g2 ;\
796 stxa %l1, [%sp + %g2]asi_num ;\
803 stxa %l5, [%g5 + %g2]asi_num ;\
808 stxa %i1, [%g5 + %g2]asi_num ;\
813 stxa %i5, [%g5 + %g2]asi_num ;\
882 or %g0, P_UTRAP4, %g2 ;\
894 or %g0, P_UTRAP10, %g2 ;\
906 or %g0, P_UTRAP11, %g2 ;\
966 rdpr %tpc, %g2 ;\
975 ldxa [MMU_TAG_ACCESS]%asi, %g2 ;\
983 ldxa [MMU_SFAR]%asi, %g2 ;\
990 ldxa [MMU_SFAR]%asi, %g2 ;\
1002 ldxa [MMU_SFAR]%asi, %g2 ;\
1011 ldxa [MMU_SFAR]%asi, %g2 ;\
1023 * g2 = tag access register
1032 ldxa [%g1]ASI_DMMU, %g2 ;\
1035 and %g2, %g4, %g3 /* g3 = ctx */ ;\
1040 andn %g2, %g4, %g1 /* ctx = primary */ ;\
1077 ldxa [%g6]ASI_DMMU, %g2 /* g2 = tag access */ ;\
1078 sllx %g2, TAGACC_CTX_LSHIFT, %g3 ;\
1082 srax %g2, PREDISM_BASESHIFT, %g6 /* g6 > 0 ISM predicted */ ;\
1084 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
1114 ldxa [%g6]ASI_DMMU, %g2 /* g2 = tag access */ ;\
1115 sllx %g2, TAGACC_CTX_LSHIFT, %g3 ;\
1119 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
1170 ldxa [%g6]ASI_IMMU, %g2 /* g2 = tag access */ ;\
1171 sllx %g2, TAGACC_CTX_LSHIFT, %g3 ;\
1175 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
1207 ldxa [%g6]ASI_IMMU, %g2 /* g2 = tag access */ ;\
1208 sllx %g2, TAGACC_CTX_LSHIFT, %g3 ;\
1212 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
1251 * g2 = tag access register ;\
1283 * g2 = tag access register (in)
1298 stxa %g2, [%g3 + TRAP_ENT_SP]%asi /* tag access */ ;\
1595 * g2 = tag access register (in)
1604 ldxa [%g4]ASI_IMMU, %g2 ! arg1 = addr
1631 or %g2, %g0, %g7
1738 ldx [%g1 + CPU_TMP1], %g2
1771 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step
1773 brz,pt %g2, 1f
1776 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast
1778 brz,pt %g2, 1f
1780 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast
1811 smul %g1, CPTRSIZE, %g2
1831 ldn [%g5 + %g2], %g5
1858 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step
1860 brz,pt %g2, 1f
1863 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast
1865 brz,pt %g2, 1f
1867 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast
1869 rdpr %tstate, %g2 ! cwp for trap handler
1871 bclr TSTATE_CWP_MASK, %g2
1872 wrpr %g2, %g4, %tstate
1901 ldx [%g1 + CPU_TMP1], %g2
1917 * %g2 %fsr
1934 srl %g2, FSR_FTT_SHIFT, %g7 ! extract ftt from %fsr
1939 andcc %g2, %g5, %g0
2097 * Note that we need to pass %fsr in %g2 (already read above).
2151 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2154 mov 1, %g2
2155 stb %g2, [%g1 + P_FIXALIGNMENT]
2307 sethi %hi(fpu_exists), %g2 ! check fpu_exists
2308 ld [%g2 + %lo(fpu_exists)], %g2
2309 brz,a,pn %g2, 4f
2316 rdpr %tpc, %g2
2317 lda [%g2]ASI_AIUP, %g6 ! get the user's lddf instruction
2324 rdpr %tstate, %g2 ! %tstate in %g2
2326 srl %g2, 31, %g1 ! get asi from %tstate
2365 mov %g5, %g2 ! misaligned vaddr in %g2
2386 rdpr %tpc, %g2
2387 lda [%g2]ASI_AIUP, %g6 ! get the user's stdf instruction
2395 rdpr %tstate, %g2 ! %tstate in %g2
2397 srl %g2, 31, %g1 ! get asi from %tstate
2428 mov %g5, %g2 ! misaligned vaddr in %g2
2436 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4
2438 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0
2440 mov 1, %g2
2441 st %g2, [%g1]
2447 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4
2449 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0
2455 CPU_ADDR(%g1, %g2)
2460 set PSR_ICC, %g2
2461 and %o0, %g2, %o0 ! mask out the rest
2472 CPU_ADDR(%g1, %g2)
2479 sll %o1, PSR_ICC_SHIFT, %g2
2481 and %g2, %g3, %g2 ! mask out rest
2482 sllx %g2, PSR_TSTATE_CC_SHIFT, %g2
2485 or %g3, %g2, %g3 ! or in new bits
2503 set PSR_ICC, %g2
2504 and %o0, %g2, %o0 ! mask out the rest
2507 and %g1, FPRS_FEF, %g2 ! mask out dirty upper/lower
2508 sllx %g2, PSR_FPRS_FEF_SHIFT, %g2 ! shift fef to V8 psr.ef
2509 or %o0, %g2, %o0 ! or result into psr.ef
2511 set V9_PSR_IMPLVER, %g2 ! SI assigned impl/ver: 0xef
2512 or %o0, %g2, %o0 ! or psr.impl/ver
2524 ! setx TSTATE_V8_UBITS, %g2
2526 sllx %g3, TSTATE_CCR_SHIFT, %g2
2528 andn %g1, %g2, %g1 ! zero current user bits
2529 set PSR_ICC, %g2
2530 and %g2, %o0, %g2 ! clear all but psr.icc bits
2531 sllx %g2, PSR_TSTATE_CC_SHIFT, %g3 ! shift to tstate.ccr.icc
2534 set PSR_EF, %g2
2535 and %g2, %o0, %g2 ! clear all but fp enable bit
2536 srlx %g2, PSR_FPRS_FEF_SHIFT, %g4 ! shift ef to V9 fprs.fef
2539 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1
2540 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2541 ldn [%g2 + T_LWP], %g3 ! load klwp pointer
2542 ldn [%g3 + LWP_FPU], %g2 ! get lwp_fpu pointer
2543 stuw %g4, [%g2 + FPU_FPRS] ! write fef value to fpu_fprs
2545 stub %g4, [%g2 + FPU_EN] ! write fef value to fpu_en
2555 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2557 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2558 ldn [%g2 + T_LPL], %g2 ! load lpl pointer
2559 ld [%g2 + LPL_LGRPID], %g1 ! load lpl_lgrpid
2568 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2569 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2570 ldn [%g2 + T_LWP], %g2 ! load klwp pointer
2571 ld [%g2 + PCB_TRAP0], %g2 ! lwp->lwp_pcb.pcb_trap0addr
2572 brz,pn %g2, 1f ! has it been set?
2576 wrpr %g0, %g2, %tnpc ! setup tnpc
2610 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2611 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2612 ldn [%g2 + T_LWP], %g2 ! load klwp pointer
2620 st %l1, [%g2 + PCB_TRAP0] ! lwp->lwp_pcb.pcb_trap0addr
2680 ldxa [MMU_TAG_ACCESS]%asi, %g2
2784 set obp_bpt, %g2
2808 jmp %g2
2847 * g2 = tag access register (in)
2864 * g2 = tag access register (in)
2876 stxa %g2, [%g5 + TRAP_ENT_SP]%asi ! tag access
2903 * g2 = tag access register (in)
2917 stxa %g2, [%g1 + TRAP_ENT_SP]%asi ! tag access reg
3033 CPU_ADDR(%g2, %g1) /* load CPU struct addr to %g2 */ ;\
3034 ldn [%g2 + CPU_THREAD], %g3 /* load thread pointer */ ;\
3049 * %g2: address of CPU structure \