Lines Matching refs:g1
81 * %g1 kernel trap handler
125 set trap, %g1 ;\
157 set trap, %g1 ;\
177 set (which), %g1 ;\
199 set trap, %g1 ;\
235 rdpr %tstate, %g1 ;\
236 btst TSTATE_PRIV, %g1 ;\
239 set trap, %g1 ;\
250 set dtrace_pid_probe, %g1 ;\
257 set dtrace_return_probe, %g1 ;\
339 mov 4, %g1 ;\
340 sta %l1, [%sp + %g1]asi_num ;\
347 sta %l5, [%g4 + %g1]asi_num ;\
352 sta %i1, [%g4 + %g1]asi_num ;\
357 sta %i5, [%g4 + %g1]asi_num ;\
443 mov 4, %g1 ;\
446 lda [%sp + %g1]asi_num, %l1 ;\
452 lda [%g4 + %g1]asi_num, %l5 ;\
457 lda [%g4 + %g1]asi_num, %i1 ;\
462 lda [%g4 + %g1]asi_num, %i5 ;\
542 mov 0 + V9BIAS64, %g1 ;\
543 2: stxa %l0, [%sp + %g1]asi_num ;\
551 stxa %l4, [%g5 + %g1]asi_num ;\
556 stxa %i0, [%g5 + %g1]asi_num ;\
561 stxa %i4, [%g5 + %g1]asi_num ;\
641 mov V9BIAS64 + 0, %g1 ;\
643 ldxa [%sp + %g1]asi_num, %l0 ;\
651 ldxa [%g5 + %g1]asi_num, %l4 ;\
656 ldxa [%g5 + %g1]asi_num, %i0 ;\
661 ldxa [%g5 + %g1]asi_num, %i4 ;\
764 mov 4, %g1 ;\
765 sta %l1, [%sp + %g1]asi_num ;\
772 sta %l5, [%g4 + %g1]asi_num ;\
777 sta %i1, [%g4 + %g1]asi_num ;\
782 sta %i5, [%g4 + %g1]asi_num ;\
793 mov 0 + V9BIAS64, %g1 ;\
794 stxa %l0, [%sp + %g1]asi_num ;\
802 stxa %l4, [%g5 + %g1]asi_num ;\
807 stxa %i0, [%g5 + %g1]asi_num ;\
812 stxa %i4, [%g5 + %g1]asi_num ;\
947 ldxa [%g0]ASI_INTR_RECEIVE_STATUS, %g1 ;\
948 btst IRSR_BUSY, %g1 ;\
969 mov T_INSTR_EXCEPTION, %g1 ;\
978 mov T_DATA_EXCEPTION, %g1 ;\
1030 mov MMU_TAG_ACCESS, %g1 ;\
1032 ldxa [%g1]ASI_DMMU, %g2 ;\
1040 andn %g2, %g4, %g1 /* ctx = primary */ ;\
1046 or %g1, DEMAP_SECOND, %g1 ;\
1047 or %g1, DEMAP_NUCLEUS, %g1 ;\
1048 1: stxa %g0, [%g1]ASI_DTLB_DEMAP /* MMU_DEMAP_PAGE */ ;\
1076 ldxa [%g0]ASI_DMMU_TSB_8K, %g1 /* g1 = tsbe ptr */ ;\
1085 ldda [%g1]ASI_QUAD_LDD_PHYS, %g4 /* g4 = tag, %g5 data */;\
1113 ldxa [%g0]ASI_DMMU_TSB_8K, %g1 /* g1 = tsbe ptr */ ;\
1120 brlz,pn %g1, sfmmu_udtlb_slowpath ;\
1122 ldda [%g1]ASI_NQUAD_LD, %g4 /* g4 = tag, %g5 data */ ;\
1169 ldxa [%g0]ASI_IMMU_TSB_8K, %g1 /* g1 = tsbe ptr */ ;\
1176 ldda [%g1]ASI_QUAD_LDD_PHYS, %g4 /* g4 = tag, g5 = data */ ;\
1206 ldxa [%g0]ASI_IMMU_TSB_8K, %g1 /* g1 = tsbe ptr */ ;\
1213 brlz,pn %g1, sfmmu_uitlb_slowpath /* if >1 TSB branch */ ;\
1215 ldda [%g1]ASI_NQUAD_LD, %g4 /* g4 = tag, g5 = data */ ;\
1250 * g1 = ???? ;\
1256 /* clobbers g1 and g6 */ ;\
1257 ldxa [%g0]ASI_DMMU_TSB_8K, %g1 /* g1 = tsbe ptr */ ;\
1282 * g1 = tsbe pointer (in/clobbered)
1302 stxa %g1, [%g3 + TRAP_ENT_F3]%asi /* tsb pointer */ ;\
1311 ldxa [%g0]ASI_IMMU, %g1 /* tag target */ ;\
1314 movne %icc, %g4, %g1 ;\
1315 stxa %g1, [%g3 + TRAP_ENT_TSTATE]%asi /* tsb tag */ ;\
1503 mov PTL1_BAD_DEBUG, %g1; GOTO(ptl1_panic);
1594 * g1 = tsbe pointer (in/clobbered)
1606 set trap, %g1
1611 rdpr %tstate, %g1
1612 btst TSTATE_PRIV, %g1
1615 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1616 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer
1617 ldn [%g1 + T_PROCP], %g1 ! load proc pointer
1618 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps?
1634 mov T_ALIGNMENT, %g1
1637 rdpr %tstate, %g1
1638 btst TSTATE_PRIV, %g1
1641 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1642 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer
1643 ldn [%g1 + T_PROCP], %g1 ! load proc pointer
1644 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps?
1651 mov T_PRIV_INSTR, %g1
1678 cmp %g1, T_INSTR_EXCEPTION ! branch to the itlb or
1682 cmp %g1, T_DATA_EXCEPTION ! to a IMMU exception
1687 or %g3, %g1, %g3
1688 set trap, %g1
1696 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1697 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer
1699 brz,a,pn %g1, 2f
1709 mov PTL1_BAD_FPTRAP, %g1
1711 ldn [%g1 + T_PROCP], %g1 ! load proc pointer
1712 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps?
1727 set fp_disabled, %g1
1732 rdpr %tstate, %g1
1733 btst TSTATE_PRIV, %g1
1735 mov PTL1_BAD_FPTRAP, %g1
1736 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1737 stx %fsr, [%g1 + CPU_TMP1]
1738 ldx [%g1 + CPU_TMP1], %g2
1739 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer
1740 ldn [%g1 + T_PROCP], %g1 ! load proc pointer
1741 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps?
1748 set _fp_ieee_exception, %g1
1758 set trap, %g1 ! setup in case we go
1769 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1770 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer
1771 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step
1776 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast
1777 ldn [%g1 + T_DTRACE_NPC], %l2 ! arg1 = t->t_dtrace_npc (step)
1779 st %g0, [%g1 + T_DTRACE_FT] ! zero all pid provider flags
1780 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast
1784 rdpr %tstate, %g1 ! cwp for trap handler
1786 bclr TSTATE_CWP_MASK, %g1
1787 wrpr %g1, %g4, %tstate
1793 rdpr %tstate, %g1
1794 btst TSTATE_PRIV, %g1
1797 CPU_ADDR(%g4, %g1) ! load CPU struct addr
1809 sub %g3, 254, %g1 ! UT_TRAP_INSTRUCTION_16 = p_utraps[18]
1811 smul %g1, CPTRSIZE, %g2
1820 mov 1, %g1
1821 st %g1, [%g4 + CPU_TL1_HDLR] ! set CPU_TL1_HDLR
1822 rdpr %tpc, %g1 ! ld trapping instruction using
1823 lduwa [%g1]ASI_AIUP, %g1 ! "AS IF USER" ASI which could fault
1827 andcc %g1, %g4, %g4 ! and instruction with mask
1828 bnz,a,pt %icc, 3f ! if %g4 == zero, %g1 is an ILLTRAP
1835 set trap, %g1
1845 set trap, %g1 ! setup in case we go
1856 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1857 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer
1858 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step
1863 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast
1864 ldn [%g1 + T_DTRACE_NPC], %l7 ! arg1 == t->t_dtrace_npc (step)
1866 st %g0, [%g1 + T_DTRACE_FT] ! zero all pid provider flags
1867 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast
1874 ldn [%g1 + T_PROCP], %g4 ! load proc pointer
1880 ldn [%g1 + T_LWP], %g1 ! load klwp pointer
1881 ld [%g1 + PCB_STEP], %g4 ! load single-step flag
1885 stn %g5, [%g1 + PCB_TRACEPC] ! save trap handler addr in pcb
1899 CPU_ADDR(%g1, %g4)
1900 stx %fsr, [%g1 + CPU_TMP1]
1901 ldx [%g1 + CPU_TMP1], %g2
1916 * %g1 per cpu address
1944 st %g7, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag
1946 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag
1971 std %d62, [%g1 + CPU_TMP1] ! save original value
2062 ldd [%g1 + CPU_TMP1], %d62 ! restore %d62
2100 set _fp_exception, %g1
2107 set trap, %g1
2151 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2152 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer
2153 ldn [%g1 + T_PROCP], %g1
2155 stb %g2, [%g1 + P_FIXALIGNMENT]
2312 CPU_ADDR(%g1, %g4)
2314 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag
2318 srl %g6, 23, %g1 ! using ldda or not?
2319 and %g1, 1, %g1
2320 brz,a,pt %g1, 2f ! check for ldda instruction
2322 srl %g6, 13, %g1 ! check immflag
2323 and %g1, 1, %g1
2325 brnz,a,pn %g1, 1f
2326 srl %g2, 31, %g1 ! get asi from %tstate
2327 srl %g6, 5, %g1 ! get asi from instruction
2328 and %g1, 0xFF, %g1 ! imm_asi field
2330 cmp %g1, ASI_P ! primary address space
2333 cmp %g1, ASI_PNF ! primary no fault address space
2336 cmp %g1, ASI_S ! secondary address space
2339 cmp %g1, ASI_SNF ! secondary no fault address space
2349 CPU_ADDR(%g7, %g1) ! save data on a per-cpu basis
2356 CPU_ADDR(%g1, %g4)
2357 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag
2360 CPU_ADDR(%g1, %g4)
2361 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag
2366 set fpu_trap, %g1 ! goto C for the little and
2382 CPU_ADDR(%g1, %g4)
2384 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag
2389 srl %g6, 23, %g1 ! using stda or not?
2390 and %g1, 1, %g1
2391 brz,a,pt %g1, 2f ! check for stda instruction
2393 srl %g6, 13, %g1 ! check immflag
2394 and %g1, 1, %g1
2396 brnz,a,pn %g1, 1f
2397 srl %g2, 31, %g1 ! get asi from %tstate
2398 srl %g6, 5, %g1 ! get asi from instruction
2399 and %g1, 0xFF, %g1 ! imm_asi field
2401 cmp %g1, ASI_P ! primary address space
2404 cmp %g1, ASI_S ! secondary address space
2410 CPU_ADDR(%g7, %g1)
2419 CPU_ADDR(%g1, %g4)
2420 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag
2423 CPU_ADDR(%g1, %g4)
2424 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag
2429 set fpu_trap, %g1 ! goto C for the little and
2436 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4
2438 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0
2439 set trap_freeze, %g1
2441 st %g2, [%g1]
2445 set trap_freeze, %g1
2446 st %g0, [%g1]
2447 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4
2449 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0
2455 CPU_ADDR(%g1, %g2)
2456 stx %o0, [%g1 + CPU_TMP1] ! save %o0
2457 stx %o1, [%g1 + CPU_TMP2] ! save %o1
2465 mov %o0, %g1 ! move ccr to normal %g1
2467 ldx [%g1 + CPU_TMP1], %o0 ! restore %o0
2468 ldx [%g1 + CPU_TMP2], %o1 ! restore %o1
2472 CPU_ADDR(%g1, %g2)
2473 stx %o0, [%g1 + CPU_TMP1] ! save %o0
2474 stx %o1, [%g1 + CPU_TMP2] ! save %o1
2477 mov %g1, %o1
2487 ldx [%g1 + CPU_TMP1], %o0 ! restore %o0
2488 ldx [%g1 + CPU_TMP2], %o1 ! restore %o1
2501 rdpr %tstate, %g1 ! get tstate
2502 srlx %g1, PSR_TSTATE_CC_SHIFT, %o0 ! shift ccr to V8 psr
2506 rd %fprs, %g1 ! get fprs
2507 and %g1, FPRS_FEF, %g2 ! mask out dirty upper/lower
2523 rdpr %tstate, %g1 ! get tstate
2528 andn %g1, %g2, %g1 ! zero current user bits
2532 wrpr %g1, %g3, %tstate ! write tstate
2539 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1
2540 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2555 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2556 ld [%g1 + CPU_ID], %o0 ! load cpu_id
2557 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2559 ld [%g2 + LPL_LGRPID], %g1 ! load lpl_lgrpid
2560 sra %g1, 0, %o1
2568 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2569 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2573 st %l0, [%g1 + CPU_TMP1] ! delay - save some locals
2574 st %l1, [%g1 + CPU_TMP2]
2583 ! Note that %g1 still contains CPU struct addr
2584 ld [%g1 + CPU_TMP2], %l1 ! restore locals
2585 ld [%g1 + CPU_TMP1], %l0
2588 mov %g1, %l0
2589 st %l1, [%g1 + CPU_TMP2]
2596 cmp %g1, OSYS_mmap ! compare to old 4.x mmap
2597 movz %icc, SYS_mmap, %g1
2610 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2611 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2613 st %l0, [%g1 + CPU_TMP1] ! save some locals
2614 st %l1, [%g1 + CPU_TMP2]
2617 mov %g1, %l1
2621 ld [%g1 + CPU_TMP1], %l0 ! restore locals
2622 ld [%g1 + CPU_TMP2], %l1
2683 mov T_DATA_EXCEPTION, %g1
2729 mov PTL1_BAD_MMUTRAP, %g1
2735 mov PTL1_BAD_MMUTRAP, %g1
2739 mov PTL1_BAD_MMUTRAP, %g1
2760 jmp %g1 + 0
2767 jmp %g1 + 0
2787 mov MMU_PCONTEXT, %g1
2788 ldxa [%g1]ASI_DMMU, %g1
2789 srlx %g1, CTXREG_NEXT_SHIFT, %g3
2793 btst %g4, %g1
2796 xor %g3, %g1, %g3 ! user: clr N_pgsz0/1 bits
2798 set DEMAP_ALL_TYPE, %g1
2799 stxa %g0, [%g1]ASI_DTLB_DEMAP
2800 stxa %g0, [%g1]ASI_ITLB_DEMAP
2801 mov MMU_PCONTEXT, %g1
2802 stxa %g3, [%g1]ASI_DMMU
2804 sethi %hi(FLUSH_ADDR), %g1
2805 flush %g1 ! flush required by immu
2846 * g1 = tsbe pointer (in/clobbered)
2863 * g1 = tsb8k pointer (in)
2882 stna %g1, [%g5 + TRAP_ENT_F3]%asi ! tsb8k pointer
2883 srlx %g1, 32, %g6
2910 TRACE_PTR(%g1, %g6)
2912 stxa %g6, [%g1 + TRAP_ENT_TICK]%asi
2914 stna %g6, [%g1 + TRAP_ENT_TPC]%asi
2916 stxa %g6, [%g1 + TRAP_ENT_TSTATE]%asi
2917 stxa %g2, [%g1 + TRAP_ENT_SP]%asi ! tag access reg
2918 stxa %g0, [%g1 + TRAP_ENT_TR]%asi
2919 stxa %g0, [%g1 + TRAP_ENT_F1]%asi
2920 stxa %g0, [%g1 + TRAP_ENT_F2]%asi
2921 stxa %g0, [%g1 + TRAP_ENT_F3]%asi
2922 stxa %g0, [%g1 + TRAP_ENT_F4]%asi
2924 stha %g6, [%g1 + TRAP_ENT_TL]%asi
2926 stha %g6, [%g1 + TRAP_ENT_TT]%asi
2927 TRACE_NEXT(%g1, %g4, %g5)
3014 set fast_trap_dummy_call, %g1
3033 CPU_ADDR(%g2, %g1) /* load CPU struct addr to %g2 */ ;\
3048 * %g1: return address (where the brand handler jumps back to) \
3052 mov %pc, %g1 ;\
3053 add %g1, 16, %g1 ;\