Cross Reference: /illumos-gate/usr/src/uts/sun4u/io/px/px

Lines Matching refs:ull
46  * LPU_RESET should be set to 0ull during resume
101  * MMU_TTE_CACHE_INVALIDATE needs to be cleared. (-1ull)
125  * JBC_ERROR_STATUS_CLEAR needs to be cleared. (-1ull)
139  * UBC_ERROR_STATUS_CLEAR needs to be cleared. (-1ull)
228 	CSR_XS(xbc_csr_base, JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE, -1ull);
259 	CSR_XS(xbc_csr_base, UBC_ERROR_LOG_ENABLE, -1ull);
266 	CSR_XS(xbc_csr_base, UBC_ERROR_STATUS_CLEAR, -1ull);
374 		val &= ~(1ull << TLU_CONTROL_NPWR_EN);
384 	val |= (1ull << TLU_REMAIN_DETECT_QUIET);
595 	val = (1ull << TLU_LINK_CONTROL_CLOCK);
796 	val = 0ull;
902 	val = (1ull << LPU_LINK_LAYER_CONFIG_VC0_EN);
955 	val = (1ull << LPU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_NP_EN) |
956 	    (1ull << LPU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_P_EN);
1399 	val = 0ull;
1520 	CSR_XS(csr_base, DLU_INTERRUPT_MASK, 0ull);
1524 	val = (1ull << DLU_LINK_LAYER_CONFIG_VC0_EN);
1529 	val = (1ull << DLU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_NP_EN) |
1530 	    (1ull << DLU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_P_EN);
1555 	val = -1ull;
1612 	val = -1ull;
1723 	CSR_XS(csr_base, MMU_TTE_CACHE_INVALIDATE, -1ull);
1746 	val |= ((1ull << MMU_CONTROL_AND_STATUS_SE)
1750 	    | (1ull << MMU_CONTROL_AND_STATUS_BE)
1751 	    | (1ull << MMU_CONTROL_AND_STATUS_TE));
2763 	CSR_XS((caddr_t)dev_hdl, MMU_TTE_CACHE_INVALIDATE, -1ull);
2772 	CSR_XS((caddr_t)dev_hdl, LPU_RESET, 0ull);
2865 		CSR_XS((caddr_t)xbus_dev_hdl, UBC_ERROR_STATUS_CLEAR, -1ull);
2875 		CSR_XS((caddr_t)xbus_dev_hdl, JBC_ERROR_STATUS_CLEAR, -1ull);
2994 	if (reg & (1ull << TLU_PME_TURN_OFF_GENERATE_PTO)) {
3001 	reg |= (1ull << TLU_PME_TURN_OFF_GENERATE_PTO);
3038 	if (!(reg & (1ull << TLU_REMAIN_DETECT_QUIET))) {
3051 	reg &= ~(1ull << TLU_REMAIN_DETECT_QUIET);
3063 	tlu_ctrl |= (1ull << TLU_REMAIN_DETECT_QUIET);
3078 	if (!(reg & (1ull << ILU_ERROR_LOG_ENABLE_SPARE3))) {
3092 	if (!(reg & (1ull << TLU_SLOT_STATUS_PSD)) ||
3093 	    (reg & (1ull << TLU_SLOT_STATUS_MRLS))) {
3167 		    (reg & (1ull << DLU_LINK_LAYER_STATUS_DLUP_STS)) &&
3196 	if (px_tlu_oe_log_mask & (1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_P))
3197 		reg |= 1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_P;
3198 	if (px_tlu_oe_log_mask & (1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_P))
3199 		reg |= 1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_P;
3200 	if (px_tlu_oe_log_mask & (1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_S))
3201 		reg |= 1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_S;
3202 	if (px_tlu_oe_log_mask & (1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_S))
3203 		reg |= 1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_S;
3285 	reg &= ~((1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_P) |
3286 	    (1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_P) |
3287 	    (1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_S) |
3288 	    (1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_S));
3372 	volatile uint64_t val = -1ull;
3383 		    (1ull << HOTPLUG_CONTROL_PWREN)) ?
3427 			    (1ull << TLU_SLOT_STATUS_PWFD);
3476 			reg &= ~((1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_P) |
3477 			    (1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_P) |
3478 			    (1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_S) |
3479 			    (1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_S));