Lines Matching defs:pxu_p
169 static uint64_t msiq_suspend(devhandle_t dev_hdl, pxu_t *pxu_p);
170 static void msiq_resume(devhandle_t dev_hdl, pxu_t *pxu_p);
171 static void jbc_init(caddr_t xbc_csr_base, pxu_t *pxu_p);
172 static void ubc_init(caddr_t xbc_csr_base, pxu_t *pxu_p);
182 hvio_cb_init(caddr_t xbc_csr_base, pxu_t *pxu_p)
184 switch (PX_CHIP_TYPE(pxu_p)) {
186 ubc_init(xbc_csr_base, pxu_p);
189 jbc_init(xbc_csr_base, pxu_p);
193 PX_CHIP_TYPE(pxu_p));
203 jbc_init(caddr_t xbc_csr_base, pxu_t *pxu_p)
254 ubc_init(caddr_t xbc_csr_base, pxu_t *pxu_p)
291 hvio_ib_init(caddr_t csr_base, pxu_t *pxu_p)
314 ilu_init(caddr_t csr_base, pxu_t *pxu_p)
337 tlu_init(caddr_t csr_base, pxu_t *pxu_p)
373 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON)
728 lpu_init(caddr_t csr_base, pxu_t *pxu_p)
1516 dlu_init(caddr_t csr_base, pxu_t *pxu_p)
1547 dmc_init(caddr_t csr_base, pxu_t *pxu_p)
1586 hvio_pec_init(caddr_t csr_base, pxu_t *pxu_p)
1590 ilu_init(csr_base, pxu_p);
1591 tlu_init(csr_base, pxu_p);
1593 switch (PX_CHIP_TYPE(pxu_p)) {
1595 dlu_init(csr_base, pxu_p);
1598 lpu_init(csr_base, pxu_p);
1602 PX_CHIP_TYPE(pxu_p));
1606 dmc_init(csr_base, pxu_p);
1630 mmu_tte_to_pa(uint64_t tte, pxu_t *pxu_p)
1634 switch (PX_CHIP_TYPE(pxu_p)) {
1643 PX_CHIP_TYPE(pxu_p));
1654 mmu_bypass_noncache(pxu_t *pxu_p)
1658 switch (PX_CHIP_TYPE(pxu_p)) {
1668 PX_CHIP_TYPE(pxu_p));
1680 mmu_tsb_entries(caddr_t csr_base, pxu_t *pxu_p)
1698 hvio_mmu_init(caddr_t csr_base, pxu_t *pxu_p)
1703 bzero(pxu_p->tsb_vaddr, pxu_p->tsb_size);
1710 obp_tsb_entries = mmu_tsb_entries(csr_base, pxu_p);
1713 pxu_p->obp_tsb_paddr = obp_tsb_pa;
1714 pxu_p->obp_tsb_entries = obp_tsb_entries;
1717 hvio_obptsb_attach(pxu_p);
1732 for (i = 8; i && (pxu_p->tsb_size < (0x2000 << i)); i--)
1735 val = (((((va_to_pa(pxu_p->tsb_vaddr)) >> 13) << 13) |
1787 hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, pages_t pages,
1797 if ((PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) &&
1810 pxu_p->tsb_vaddr[tsb_index] = MMU_PTOB(pfn) | attr;
1817 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) {
1821 (pxu_p->tsb_paddr+
1830 pxu_p->tsb_vaddr[tsb_index] = MMU_PTOB(pfn) | attr;
1837 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) {
1841 (pxu_p->tsb_paddr+
1853 hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid,
1860 pxu_p->tsb_vaddr[tsb_index] = MMU_INVALID_TTE;
1867 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) {
1871 (pxu_p->tsb_paddr+
1882 hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid,
1889 tte_addr = (uint64_t *)(pxu_p->tsb_vaddr) + tsb_index;
1892 *r_addr_p = mmu_tte_to_pa(*tte_addr, pxu_p);
1908 hvio_obptsb_attach(pxu_t *pxu_p)
1915 obp_tsb_pa = pxu_p->obp_tsb_paddr;
1916 obp_tsb_entries = pxu_p->obp_tsb_entries;
1923 base_tte_addr = pxu_p->tsb_vaddr +
1924 ((pxu_p->tsb_size >> 3) - obp_tsb_entries);
1950 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p;
1954 obp_tsb_pa = pxu_p->obp_tsb_paddr;
1955 obp_tsb_entries = pxu_p->obp_tsb_entries;
1962 obp_tsb_bias = (pxu_p->tsb_size >> 3) - obp_tsb_entries;
1980 hvio_get_bypass_base(pxu_t *pxu_p)
1984 switch (PX_CHIP_TYPE(pxu_p)) {
1994 PX_CHIP_TYPE(pxu_p));
2003 hvio_get_bypass_end(pxu_t *pxu_p)
2007 switch (PX_CHIP_TYPE(pxu_p)) {
2017 PX_CHIP_TYPE(pxu_p));
2026 hvio_iommu_getbypass(devhandle_t dev_hdl, pxu_t *pxu_p, r_addr_t ra,
2031 *io_addr_p = hvio_get_bypass_base(pxu_p) | ra |
2032 (pf_is_memory(pfn) ? 0 : mmu_bypass_noncache(pxu_p));
2047 hvio_intr_devino_to_sysino(devhandle_t dev_hdl, pxu_t *pxu_p, devino_t devino,
2055 *sysino = DEVINO_TO_SYSINO(pxu_p->portid, devino);
2172 hvio_intr_gettarget(devhandle_t dev_hdl, pxu_t *pxu_p, sysino_t sysino,
2175 switch (PX_CHIP_TYPE(pxu_p)) {
2186 "unknown chip type: 0x%x\n", PX_CHIP_TYPE(pxu_p));
2198 hvio_intr_settarget(devhandle_t dev_hdl, pxu_t *pxu_p, sysino_t sysino,
2211 switch (PX_CHIP_TYPE(pxu_p)) {
2229 "unknown chip type: 0x%x\n", PX_CHIP_TYPE(pxu_p));
2246 hvio_msiq_init(devhandle_t dev_hdl, pxu_t *pxu_p)
2249 (uint64_t)pxu_p->msiq_mapped_p);
2255 (uint64_t)ID_TO_IGN(PX_CHIP_TYPE(pxu_p),
2256 pxu_p->portid) << INO_BITS);
2671 hvio_suspend(devhandle_t dev_hdl, pxu_t *pxu_p)
2677 if (msiq_suspend(dev_hdl, pxu_p) != H_EOK)
2697 pxu_p->pec_config_state = config_state;
2699 if ((pec_config_state_regs[i].chip == PX_CHIP_TYPE(pxu_p)) ||
2701 pxu_p->pec_config_state[i] =
2708 pxu_p->mmu_config_state = pxu_p->pec_config_state + PEC_KEYS;
2710 pxu_p->mmu_config_state[i] =
2715 pxu_p->ib_intr_map = pxu_p->mmu_config_state + MMU_KEYS;
2717 pxu_p->ib_intr_map[i] =
2722 pxu_p->ib_config_state = pxu_p->ib_intr_map + INTERRUPT_MAPPING_ENTRIES;
2724 pxu_p->ib_config_state[i] =
2732 hvio_resume(devhandle_t dev_hdl, devino_t devino, pxu_t *pxu_p)
2740 if (!pxu_p->pec_config_state) {
2747 pxu_p->ib_config_state[i]);
2758 pxu_p->ib_intr_map[i]);
2767 pxu_p->mmu_config_state[i]);
2775 if ((pec_config_state_regs[i].chip == PX_CHIP_TYPE(pxu_p)) ||
2778 pxu_p->pec_config_state[i]);
2783 if ((ret = hvio_intr_devino_to_sysino(dev_hdl, pxu_p, devino,
2798 kmem_free(pxu_p->pec_config_state, total_size);
2800 pxu_p->pec_config_state = NULL;
2801 pxu_p->mmu_config_state = NULL;
2802 pxu_p->ib_config_state = NULL;
2803 pxu_p->ib_intr_map = NULL;
2805 msiq_resume(dev_hdl, pxu_p);
2809 hvio_cb_suspend(devhandle_t dev_hdl, pxu_t *pxu_p)
2814 switch (PX_CHIP_TYPE(pxu_p)) {
2827 PX_CHIP_TYPE(pxu_p));
2838 pxu_p->xcb_config_state = config_state;
2840 pxu_p->xcb_config_state[i] =
2849 devino_t devino, pxu_t *pxu_p)
2856 switch (PX_CHIP_TYPE(pxu_p)) {
2879 PX_CHIP_TYPE(pxu_p));
2883 ASSERT(pxu_p->xcb_config_state);
2888 pxu_p->xcb_config_state[i]);
2892 if ((ret = hvio_intr_devino_to_sysino(pci_dev_hdl, pxu_p, devino,
2906 kmem_free(pxu_p->xcb_config_state, cb_size);
2908 pxu_p->xcb_config_state = NULL;
2912 msiq_suspend(devhandle_t dev_hdl, pxu_t *pxu_p)
2919 if ((pxu_p->msiq_config_state = kmem_zalloc(bufsz, KM_NOSLEEP)) ==
2923 cur_p = pxu_p->msiq_config_state;
2940 msiq_resume(devhandle_t dev_hdl, pxu_t *pxu_p)
2948 cur_p = pxu_p->msiq_config_state;
2953 if ((ret = hvio_msiq_init(dev_hdl, pxu_p)) != H_EOK) {
2978 kmem_free(pxu_p->msiq_config_state, bufsz);
2979 pxu_p->msiq_config_state = NULL;
3457 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p;
3460 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) {
3461 if (!CSR_BR((caddr_t)pxu_p->px_address[PX_REG_CSR],
3469 if (!CSR_BR((caddr_t)pxu_p->px_address[PX_REG_CSR],
3471 !CSR_BR((caddr_t)pxu_p->px_address[PX_REG_CSR],
3474 reg = CSR_XR((caddr_t)pxu_p->px_address[PX_REG_CSR],
3480 CSR_XS((caddr_t)pxu_p->px_address[PX_REG_CSR],
3488 regops->cookie = (void *)&pxu_p->px_address[PX_REG_CSR];
3500 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p;
3502 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON)