Lines Matching refs:pbm_p
255 pbm_t *pbm_p = pci_p->pci_pbm_p;
299 pbm_p->pbm_sync_ino = pci_p->pci_inos[CBNINTR_PBM];
300 if (ret = pbm_register_intr(pbm_p)) {
305 intr_dist_add(pbm_intr_dist, pbm_p);
331 pci_schizo_cdma_sync(pbm_t *pbm_p)
333 pci_t *pci_p = pbm_p->pbm_pci_p;
339 mutex_enter(&pbm_p->pbm_sync_mutex);
341 pbm_p->pbm_cdma_req_cnt++;
343 pbm_p->pbm_cdma_flag = PBM_CDMA_PEND;
347 while (pbm_p->pbm_cdma_flag != PBM_CDMA_DONE) {
352 if (pbm_p->pbm_cdma_flag == PBM_CDMA_DONE)
355 pbm_p->pbm_nameinst_str, pbm_p->pbm_nameaddr_str);
358 if (pbm_p->pbm_cdma_flag != PBM_CDMA_DONE)
359 pbm_p->pbm_cdma_to_cnt++;
362 pbm_p->pbm_cdma_success_cnt++;
363 pbm_p->pbm_cdma_latency_sum += start_time;
364 if (start_time > pbm_p->pbm_cdma_latency_max)
365 pbm_p->pbm_cdma_latency_max = start_time;
368 mutex_exit(&pbm_p->pbm_sync_mutex);
388 pci_pbm_dma_sync(pbm_t *pbm_p, ib_ino_t ino)
390 pci_t *pci_p = pbm_p->pbm_pci_p;
398 pci_schizo_cdma_sync(pbm_p);
402 sync_reg_pa = pbm_p->pbm_sync_reg_pa;
405 if (((chip_type == PCI_CHIP_XMITS) && (ino == pbm_p->pbm_sync_ino)) ||
408 mutex_enter(&pbm_p->pbm_sync_mutex);
426 pbm_p->pbm_nameaddr_str, sync_reg_pa, flag_val);
430 mutex_exit(&pbm_p->pbm_sync_mutex);
618 pci_pbm_intr_dist(pbm_t *pbm_p)
620 pci_t *pci_p = pbm_p->pbm_pci_p;
624 mutex_enter(&pbm_p->pbm_sync_mutex);
626 mutex_exit(&pbm_p->pbm_sync_mutex);
713 pbm_configure(pbm_t *pbm_p)
715 pci_t *pci_p = pbm_p->pbm_pci_p;
716 dev_info_t *dip = pbm_p->pbm_pci_p->pci_dip;
722 l = *pbm_p->pbm_ctrl_reg; /* save control register state */
736 pbm_p->pbm_speed = PBM_SPEED_66MHZ;
738 pbm_p->pbm_speed = PBM_SPEED_33MHZ;
740 pbm_p->pbm_speed == PBM_SPEED_66MHZ ? 66 : 33);
785 if (*pbm_p->pbm_ctrl_reg & XMITS_PCI_CTRL_X_MODE)
789 pbm_p->pbm_nameinst_str,
790 pbm_p->pbm_nameaddr_str, CHIP_VER(pci_p));
798 pcix_err = *pbm_p->pbm_pcix_err_stat_reg;
801 *pbm_p->pbm_pcix_err_stat_reg = pcix_err;
808 *pbm_p->pbm_pci_ped_ctrl = 0x3fff;
851 *pbm_p->pbm_ctrl_reg = l;
857 volatile uint64_t *ioc_csr_p = pbm_p->pbm_ctrl_reg +
876 volatile uint64_t *pbm_icd = pbm_p->pbm_ctrl_reg +
888 *pbm_p->pbm_async_flt_status_reg = l;
894 l = *pbm_p->pbm_diag_reg;
922 *pbm_p->pbm_diag_reg = l;
931 pbm_p->pbm_config_header->ch_command_reg = s;
940 pbm_p->pbm_config_header->ch_status_reg = s;
953 pbm_p->pbm_config_header->ch_latency_timer_reg =
958 (int)pbm_p->pbm_config_header->ch_latency_timer_reg);
971 *pbm_p->pbm_upper_retry_counter_reg = (uint64_t)xurc;
974 *pbm_p->pbm_upper_retry_counter_reg);
980 pbm_disable_pci_errors(pbm_t *pbm_p)
982 pci_t *pci_p = pbm_p->pbm_pci_p;
989 *pbm_p->pbm_ctrl_reg &=
1270 pbm_t *pbm_p = (pbm_t *)arg;
1273 if (pbm_p->pbm_quiesce_count > 0) {
1274 ctrl_reg_p = pbm_p->pbm_ctrl_reg;
1275 *ctrl_reg_p = pbm_p->pbm_saved_ctrl_reg;
1284 pbm_t *pbm_p = (pbm_t *)arg;
1288 if (pbm_p->pbm_quiesce_count > 0) {
1289 ctrl_reg_p = pbm_p->pbm_ctrl_reg;
1291 *ctrl_reg_p = pbm_p->pbm_saved_ctrl_reg;
1293 ctrl_reg = pbm_p->pbm_saved_ctrl_reg;
1304 pci_pbm_setup(pbm_t *pbm_p)
1306 pci_t *pci_p = pbm_p->pbm_pci_p;
1311 mutex_init(&pbm_p->pbm_sync_mutex, NULL, MUTEX_DRIVER,
1314 pbm_p->pbm_config_header = (config_header_t *)pci_p->pci_address[2];
1315 pbm_p->pbm_ctrl_reg = (uint64_t *)(a + SCHIZO_PCI_CTRL_REG_OFFSET);
1316 pbm_p->pbm_diag_reg = (uint64_t *)(a + SCHIZO_PCI_DIAG_REG_OFFSET);
1317 pbm_p->pbm_async_flt_status_reg =
1319 pbm_p->pbm_async_flt_addr_reg =
1321 pbm_p->pbm_estar_reg = (uint64_t *)(a + SCHIZO_PCI_ESTAR_REG_OFFSET);
1322 pbm_p->pbm_pcix_err_stat_reg = (uint64_t *)(a +
1324 pbm_p->pbm_pci_ped_ctrl = (uint64_t *)(a +
1341 pbm_p->pbm_panic_cb_id = callb_add(pci_pbm_panic_callb,
1342 (void *)pbm_p, CB_CL_PANIC, "pci_panic");
1343 pbm_p->pbm_debug_cb_id = callb_add(pci_pbm_panic_callb,
1344 (void *)pbm_p, CB_CL_ENTER_DEBUGGER, "pci_debug_enter");
1351 pbm_p->pbm_sync_reg_pa = pa + SCHIZO_PBM_DMA_SYNC_REG_OFFSET;
1370 pbm_p->pbm_upper_retry_counter_reg =
1373 pbm_p->pbm_sync_reg_pa = pa + PBM_DMA_SYNC_PEND_REG_OFFSET;
1377 pci_pbm_teardown(pbm_t *pbm_p)
1379 (void) callb_delete(pbm_p->pbm_panic_cb_id);
1380 (void) callb_delete(pbm_p->pbm_debug_cb_id);
2240 pbm_t *pbm_p = pci_p->pci_pbm_p;
2248 pci_cfg_stat = pbm_p->pbm_config_header->ch_status_reg;
2249 pbm_ctl_stat = *pbm_p->pbm_ctrl_reg;
2250 pbm_afsr = *pbm_p->pbm_async_flt_status_reg;
2315 pbm_t *pbm_p = pci_p->pci_pbm_p;
2345 ndi_fm_acc_err_set(pbm_p->pbm_excl_handle, derr);
2372 } else if ((*pbm_p->pbm_ctrl_reg & XMITS_PCI_CTRL_X_MODE) &&
2577 pbm_t *pbm_p = pci_p->pci_pbm_p;
2591 pbm_p->pbm_config_header->ch_status_reg;
2592 pbm_err_p->pbm_ctl_stat = *pbm_p->pbm_ctrl_reg;
2593 pbm_err_p->pbm_afsr = *pbm_p->pbm_async_flt_status_reg;
2594 pbm_err_p->pbm_afar = *pbm_p->pbm_async_flt_addr_reg;
2597 pbm_p->pbm_config_header->ch_command_reg;
2598 pbm_err_p->pbm_pci.pci_pa = *pbm_p->pbm_async_flt_addr_reg;
2626 *pbm_p->pbm_ctrl_reg =
2630 pbm_err_p->pbm_ctl_stat = *pbm_p->pbm_ctrl_reg;
2667 pbm_t *pbm_p = pci_p->pci_pbm_p;
2670 ASSERT(MUTEX_HELD(&pbm_p->pbm_pci_p->pci_common_p->pci_fm_mutex));
2672 if (*pbm_p->pbm_ctrl_reg & SCHIZO_PCI_CTRL_PCI_MMU_ERR) {
2675 pbm_p->pbm_config_header->ch_status_reg =
2677 *pbm_p->pbm_ctrl_reg = pbm_err_p->pbm_ctl_stat;
2678 *pbm_p->pbm_async_flt_status_reg = pbm_err_p->pbm_afsr;
2683 pbm_clear_error(pbm_t *pbm_p)
2693 pbm_ctl_stat = *pbm_p->pbm_ctrl_reg;
2694 pbm_afsr = *pbm_p->pbm_async_flt_status_reg;
2698 pbm_ctl_stat = *pbm_p->pbm_ctrl_reg;
2699 pbm_afsr = *pbm_p->pbm_async_flt_status_reg;
3255 pbm_t *pbm_p = pci_p->pci_pbm_p;
3269 pbm_p->pbm_anychild_cfgpa = cfgpa;
3276 pbm_t *pbm_p = pci_p->pci_pbm_p;
3292 if (pbm_p->pbm_quiesce_count > 0) {
3293 pbm_p->pbm_saved_ctrl_reg &= ~SCHIZO_PCI_CTRL_ARB_PARK;
3295 ctrl_reg_p = pbm_p->pbm_ctrl_reg;
3301 if (*pbm_p->pbm_ctrl_reg & XMITS_PCI_CTRL_X_MODE) {
3328 uint64_t tunable = (*pbm_p->pbm_ctrl_reg &
3337 ((*pbm_p->pbm_ctrl_reg & XMITS_PCI_CTRL_X_MODE)?
3444 pbm_t *pbm_p = (pbm_t *)a;
3445 pbm_p->pbm_cdma_flag = PBM_CDMA_DONE;
3447 pbm_p->pbm_cdma_intr_cnt++;
3483 pbm_t *pbm_p = pci_p->pci_pbm_p;
3487 pbm_p->pbm_cdma_imr_save = *ib_intr_map_reg_addr(pci_p->pci_ib_p, ino);
3493 pbm_t *pbm_p = pci_p->pci_pbm_p;
3497 *ib_intr_map_reg_addr(pci_p->pci_ib_p, ino) = pbm_p->pbm_cdma_imr_save;
3512 pbm_t *pbm_p;
3514 pbm_p = pci_p->pci_pbm_p;
3515 ctrl_reg_p = pbm_p->pbm_ctrl_reg;
3517 if (pbm_p->pbm_quiesce_count++ == 0) {
3522 pbm_p->pbm_saved_ctrl_reg = ctrl_reg;
3532 if (pbm_p->pbm_anychild_cfgpa)
3533 (void) ldphysio(pbm_p->pbm_anychild_cfgpa);
3550 pbm_t *pbm_p;
3555 pbm_p = pci_p->pci_pbm_p;
3556 ctrl_reg_p = pbm_p->pbm_ctrl_reg;
3558 ASSERT(pbm_p->pbm_quiesce_count > 0);
3559 if (--pbm_p->pbm_quiesce_count == 0) {
3560 *ctrl_reg_p = pbm_p->pbm_saved_ctrl_reg;