Lines Matching refs:pbm_err_p
78 static void pci_pbm_errstate_get(pci_t *pci_p, pbm_errstate_t *pbm_err_p);
82 static int pcix_ma_behind_bridge(pbm_errstate_t *pbm_err_p);
1945 pbm_errstate_t *pbm_err_p)
1947 uint32_t err_bits = pbm_err_p->pbm_err & XMITS_PCIX_MSG_INDEX_MASK;
1954 if (pbm_err_p->pbm_multi ? !(err_bits & msg_key) : err_bits
1960 pbm_err_p->pbm_pri ? "" : PCIX_SECONDARY,
1963 pbm_err_p->pbm_err_class = buf;
1964 pcix_ereport_post(dip, ena, pbm_err_p);
1975 pcix_log_split_err(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err_p)
1977 uint32_t class = pbm_err_p->pbm_err & XMITS_PCIX_MSG_CLASS_MASK;
1984 pbm_err_p->pbm_multi = PCIX_SINGLE_ERR;
1986 pcix_split_errs_tbl[i], pbm_err_p);
1999 pcix_log_pbm(pci_t *pci_p, uint64_t ena, pbm_errstate_t *pbm_err_p)
2009 pbm_err_p->pbm_ctl_stat, pbm_err_p->pbm_afsr);
2012 !(pbm_err_p->pbm_ctl_stat & XMITS_PCI_CTRL_X_MODE))
2015 if (pbm_err_p->pbm_afsr & XMITS_PCI_X_AFSR_P_SC_ERR) {
2016 pbm_err_p->pbm_err = PBM_AFSR_TO_PRISPLIT(pbm_err_p->pbm_afsr);
2017 pbm_err_p->pbm_pri = PBM_PRIMARY;
2018 pcix_log_split_err(pci_p->pci_dip, ena, pbm_err_p);
2021 if (pbm_err_p->pbm_afsr & XMITS_PCI_X_AFSR_S_SC_ERR) {
2022 pbm_err_p->pbm_err = PBM_AFSR_TO_PRISPLIT(pbm_err_p->pbm_afsr);
2023 pbm_err_p->pbm_pri = PBM_PRIMARY;
2024 pcix_log_split_err(pci_p->pci_dip, ena, pbm_err_p);
2028 e = PBM_PCIX_TO_PRIERR(pbm_err_p->pbm_pcix_stat);
2030 pbm_err_p->pbm_pri = PBM_PRIMARY;
2031 pbm_err_p->pbm_err = e;
2032 pbm_err_p->pbm_multi = PCIX_MULTI_ERR;
2034 pcix_stat_errs_tbl, pbm_err_p) == DDI_FM_FATAL)
2040 e = PBM_PCIX_TO_SECERR(pbm_err_p->pbm_pcix_stat);
2042 pbm_err_p->pbm_pri = PBM_SECONDARY;
2043 pbm_err_p->pbm_err = e;
2044 pbm_err_p->pbm_multi = PCIX_MULTI_ERR;
2046 pcix_stat_errs_tbl, pbm_err_p) == DDI_FM_FATAL)
2105 pci_pbm_classify(pbm_errstate_t *pbm_err_p)
2111 err = pbm_err_p->pbm_pri ? PBM_AFSR_TO_PRIERR(pbm_err_p->pbm_afsr):
2112 PBM_AFSR_TO_SECERR(pbm_err_p->pbm_afsr);
2116 (pbm_err_p->pbm_pri == pbm_err_tbl[i].pbm_pri)) {
2118 pbm_err_p->pbm_pci.pci_err_class =
2121 pbm_err_p->pbm_err_class =
2124 pbm_err_p->pbm_terr_class =
2126 pbm_err_p->pbm_log = pbm_err_tbl[i].pbm_flag;
2140 iommu_err_handler(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err_p)
2154 pbm_err_p->pbm_err_class = PCI_SCH_MMU_ERR;
2155 iommu_ereport_post(dip, ena, pbm_err_p);
2166 ta_signalled = pbm_err_p->pbm_pci.pci_cfg_stat &
2170 pbm_err_p->pbm_err_class = PCI_TOM_MMU_BAD_TSBTBW;
2172 iommu_ereport_post(dip, ena, pbm_err_p);
2180 pbm_err_p->pbm_err_class = PCI_TOM_MMU_BAD_VA;
2182 iommu_ereport_post(dip, ena, pbm_err_p);
2194 pbm_err_p->pbm_err_class = PCI_TOM_MMU_PROT_ERR;
2195 iommu_ereport_post(dip, ena, pbm_err_p);
2199 pbm_err_p->pbm_err_class = PCI_TOM_MMU_INVAL_ERR;
2205 ena, (void *)&pbm_err_p->pbm_iommu.iommu_tfar);
2215 iommu_ereport_post(dip, ena, pbm_err_p);
2218 pbm_err_p->pbm_err_class = PCI_TOM_MMU_TO_ERR;
2220 iommu_ereport_post(dip, ena, pbm_err_p);
2223 pbm_err_p->pbm_err_class = PCI_TOM_MMU_UE;
2224 iommu_ereport_post(dip, ena, pbm_err_p);
2550 pcix_ma_behind_bridge(pbm_errstate_t *pbm_err_p)
2554 if (pbm_err_p->pbm_afsr & XMITS_PCI_X_AFSR_S_SC_ERR)
2557 if (pbm_err_p->pbm_afsr & XMITS_PCI_X_AFSR_P_SC_ERR) {
2558 msg = (pbm_err_p->pbm_afsr >> XMITS_PCI_X_P_MSG_SHIFT) &
2575 pci_pbm_errstate_get(pci_t *pci_p, pbm_errstate_t *pbm_err_p)
2583 bzero(pbm_err_p, sizeof (pbm_errstate_t));
2588 pbm_err_p->pbm_bridge_type = PCI_BRIDGE_TYPE(pci_p->pci_common_p);
2590 pbm_err_p->pbm_pci.pci_cfg_stat =
2592 pbm_err_p->pbm_ctl_stat = *pbm_p->pbm_ctrl_reg;
2593 pbm_err_p->pbm_afsr = *pbm_p->pbm_async_flt_status_reg;
2594 pbm_err_p->pbm_afar = *pbm_p->pbm_async_flt_addr_reg;
2595 pbm_err_p->pbm_iommu.iommu_stat = *iommu_p->iommu_ctrl_reg;
2596 pbm_err_p->pbm_pci.pci_cfg_comm =
2598 pbm_err_p->pbm_pci.pci_pa = *pbm_p->pbm_async_flt_addr_reg;
2606 pbm_err_p->pbm_err_sl = (pbm_err_p->pbm_ctl_stat &
2618 if (pbm_err_p->pbm_ctl_stat & XMITS_PCI_CTRL_DMA_WR_PERR) {
2627 pbm_err_p->pbm_ctl_stat &
2630 pbm_err_p->pbm_ctl_stat = *pbm_p->pbm_ctrl_reg;
2639 pbm_err_p->pbm_va_log = (uint64_t)va_to_pa(
2641 pbm_err_p->pbm_iommu.iommu_tfar = *iommu_p->iommu_tfar_reg;
2648 (pbm_err_p->pbm_ctl_stat & XMITS_PCI_CTRL_X_MODE)) {
2653 pbm_err_p->pbm_pcix_stat = *pbm_pcix_stat_reg;
2654 pbm_err_p->pbm_pcix_pfar = pbm_err_p->pbm_pcix_stat &
2665 pci_clear_error(pci_t *pci_p, pbm_errstate_t *pbm_err_p)
2676 pbm_err_p->pbm_pci.pci_cfg_stat;
2677 *pbm_p->pbm_ctrl_reg = pbm_err_p->pbm_ctl_stat;
2678 *pbm_p->pbm_async_flt_status_reg = pbm_err_p->pbm_afsr;
2679 *iommu_p->iommu_ctrl_reg = pbm_err_p->pbm_iommu.iommu_stat;