Lines Matching defs:prg
108 static int pcitool_validate_barnum_bdf(pcitool_reg_t *prg);
109 static int pcitool_get_bar(pci_t *pci_p, pcitool_reg_t *prg,
112 static int pcitool_config_request(pci_t *pci_p, pcitool_reg_t *prg,
629 pcitool_reg_t prg;
642 if (ddi_copyin(arg, &prg, sizeof (pcitool_reg_t), mode) !=
655 prg.status = PCITOOL_REGPROP_NOTWELLFORMED;
662 if (prg.barnum >=
664 prg.status = PCITOOL_OUT_OF_RANGE;
669 size = PCITOOL_ACC_ATTR_SIZE(prg.acc_attr);
670 base_addr = pci_rp[prg.barnum].phys_addr;
671 max_addr = base_addr + pci_rp[prg.barnum].size;
672 prg.phys_addr = base_addr + prg.offset;
677 base_addr, prg.offset, prg.phys_addr, max_addr);
679 /* Access device. prg.status is modified. */
681 prg.phys_addr, max_addr, &prg.data, size, write_flag,
682 PCITOOL_ACC_IS_BIG_ENDIAN(prg.acc_attr), &prg.status);
688 prg.drvr_version = PCITOOL_VERSION;
689 if (ddi_copyout(&prg, arg, sizeof (pcitool_reg_t), mode) !=
700 pcitool_validate_barnum_bdf(pcitool_reg_t *prg)
704 if (prg->barnum >= (sizeof (pci_bars) / sizeof (pci_bars[0]))) {
705 prg->status = PCITOOL_OUT_OF_RANGE;
709 } else if (((prg->bus_no &
710 (PCI_REG_BUS_M >> PCI_REG_BUS_SHIFT)) != prg->bus_no) ||
711 ((prg->dev_no &
712 (PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT)) != prg->dev_no) ||
713 ((prg->func_no &
714 (PCI_REG_FUNC_M >> PCI_REG_FUNC_SHIFT)) != prg->func_no)) {
715 prg->status = PCITOOL_INVALID_ADDRESS;
723 pcitool_get_bar(pci_t *pci_p, pcitool_reg_t *prg, uint64_t config_base_addr,
738 bar_offset = PCI_BAR_OFFSET((*prg));
741 prg->barnum, bar_offset);
746 * prg->status is modified on error.
753 &prg->status);
759 prg->status = PCITOOL_INVALID_ADDRESS;
787 prg->status = PCITOOL_OUT_OF_RANGE;
791 /* Access device. prg->status is modified on error. */
797 &prg->status);
809 pcitool_config_request(pci_t *pci_p, pcitool_reg_t *prg, uint64_t base_addr,
816 prg->phys_addr = base_addr + prg->offset;
820 base_addr, prg->offset, prg->phys_addr,
821 (PCITOOL_ACC_IS_BIG_ENDIAN(prg->acc_attr)? "big" : "ltl"));
824 rval = pcitool_access(pci_p, prg->phys_addr, max_addr, &prg->data, size,
825 write_flag, PCITOOL_ACC_IS_BIG_ENDIAN(prg->acc_attr), &prg->status);
827 DEBUG1(DBG_TOOLS, dip, "config access: data:0x%llx\n", prg->data);
839 pcitool_reg_t prg;
854 if (ddi_copyin(arg, &prg, sizeof (pcitool_reg_t), mode) !=
861 prg.bus_no, prg.dev_no, prg.func_no);
863 if ((rval = pcitool_validate_barnum_bdf(&prg)) != SUCCESS)
866 size = PCITOOL_ACC_ATTR_SIZE(prg.acc_attr);
879 (prg.bus_no << PCI_REG_BUS_SHIFT) +
880 (prg.dev_no << PCI_REG_DEV_SHIFT) +
881 (prg.func_no << PCI_REG_FUNC_SHIFT);
884 prg.status = PCITOOL_OUT_OF_RANGE;
891 prg.bus_no << PCI_REG_BUS_SHIFT, prg.dev_no << PCI_REG_DEV_SHIFT,
892 prg.func_no << PCI_REG_FUNC_SHIFT, base_addr);
895 if (prg.barnum == 0) {
897 rval = pcitool_config_request(pci_p, &prg, base_addr, max_addr,
902 if (pcitool_get_bar(pci_p, &prg, base_addr, max_addr, &bar,
932 if (PCI_BAR_OFFSET(prg) == PCI_CONF_ROM) {
939 prg.status = PCITOOL_ROM_WRITE;
945 prg.status = PCITOOL_ROM_DISABLED;
962 "offset:0x%lx\n", bar, base_addr, prg.offset);
967 * Note that prg.status is modified on error.
969 prg.phys_addr = base_addr + prg.offset;
970 rval = pcitool_access(pci_p, prg.phys_addr,
971 max_addr, &prg.data, size, write_flag,
972 PCITOOL_ACC_IS_BIG_ENDIAN(prg.acc_attr), &prg.status);
976 prg.drvr_version = PCITOOL_VERSION;
977 if (ddi_copyout(&prg, arg, sizeof (pcitool_reg_t), mode) !=