Cross Reference: /illumos-gate/usr/src/uts/sun4u/io/pci/db21554.c

Lines Matching refs:config_handle
315 static void	db_pci_get_header(ddi_acc_handle_t config_handle,
317 static void	db_pci_get_conf_regs(ddi_acc_handle_t config_handle,
1450 	ddi_acc_handle_t	config_handle;
1495 		(void) pci_config_setup(child_dip, &config_handle);
1496 		db_pci_get_header(config_handle, &pci_data.pri_hdr, 0);
1500 			db_pci_get_header(config_handle,
1502 			db_pci_get_conf_regs(config_handle,
1505 		pci_config_teardown(&config_handle);
1613 db_pci_get_header(ddi_acc_handle_t config_handle, db_pci_header_t *ph,
1616 	ph->venid = pci_config_get16(config_handle, hdr_off + PCI_CONF_VENID);
1617 	ph->devid = pci_config_get16(config_handle, hdr_off + PCI_CONF_DEVID);
1618 	ph->command = pci_config_get16(config_handle, hdr_off + PCI_CONF_COMM);
1619 	ph->status = pci_config_get16(config_handle, hdr_off + PCI_CONF_STAT);
1620 	ph->revid = pci_config_get8(config_handle, hdr_off + PCI_CONF_REVID);
1621 	ph->pif = pci_config_get8(config_handle, hdr_off + PCI_CONF_PROGCLASS);
1622 	ph->subclass = pci_config_get8(config_handle,
1624 	ph->class = pci_config_get8(config_handle,
1626 	ph->cacheline = pci_config_get8(config_handle,
1628 	ph->lat = pci_config_get8(config_handle,
1630 	ph->hdr_type = pci_config_get8(config_handle,
1632 	ph->bist = pci_config_get8(config_handle, hdr_off + PCI_CONF_BIST);
1633 	ph->bar0 = pci_config_get32(config_handle, hdr_off + PCI_CONF_BASE0);
1634 	ph->bar1 = pci_config_get32(config_handle, hdr_off + PCI_CONF_BASE1);
1635 	ph->bar2 = pci_config_get32(config_handle, hdr_off + PCI_CONF_BASE2);
1636 	ph->bar3 = pci_config_get32(config_handle, hdr_off + PCI_CONF_BASE3);
1637 	ph->bar4 = pci_config_get32(config_handle, hdr_off + PCI_CONF_BASE4);
1638 	ph->bar5 = pci_config_get32(config_handle, hdr_off + PCI_CONF_BASE5);
1639 	ph->cardbus_cisp = pci_config_get32(config_handle,
1641 	ph->sub_venid = pci_config_get16(config_handle,
1643 	ph->sub_devid = pci_config_get16(config_handle,
1645 	ph->exprom_bar = pci_config_get32(config_handle,
1647 	ph->int_line = pci_config_get8(config_handle, hdr_off + PCI_CONF_ILINE);
1648 	ph->int_pin = pci_config_get8(config_handle, hdr_off + PCI_CONF_IPIN);
1649 	ph->min_gnt = pci_config_get8(config_handle, hdr_off + PCI_CONF_MIN_G);
1650 	ph->max_lat = pci_config_get8(config_handle, hdr_off + PCI_CONF_MAX_L);
1654 db_pci_get_conf_regs(ddi_acc_handle_t config_handle, db_conf_regs_t *cr)
1656 	cr->ds_mem0_tr_base = pci_config_get32(config_handle,
1658 	cr->ds_io_mem1_tr_base = pci_config_get32(config_handle,
1660 	cr->ds_mem2_tr_base = pci_config_get32(config_handle,
1662 	cr->ds_mem3_tr_base = pci_config_get32(config_handle,
1664 	cr->us_io_mem0_tr_base = pci_config_get32(config_handle,
1666 	cr->us_mem1_tr_base = pci_config_get32(config_handle,
1668 	cr->ds_mem0_setup_reg = pci_config_get32(config_handle,
1670 	cr->ds_io_mem1_setup_reg = pci_config_get32(config_handle,
1672 	cr->ds_mem2_setup_reg = pci_config_get32(config_handle,
1674 	cr->ds_mem3_setup_reg = pci_config_get64(config_handle,
1676 	cr->p_exp_rom_setup = pci_config_get32(config_handle,
1678 	cr->us_io_mem0_setup_reg = pci_config_get32(config_handle,
1680 	cr->us_mem1_setup_reg = pci_config_get32(config_handle,
1682 	cr->chip_control0 = pci_config_get16(config_handle, DB_CONF_CHIP_CTRL0);
1683 	cr->chip_control1 = pci_config_get16(config_handle, DB_CONF_CHIP_CTRL1);
1684 	cr->chip_status = pci_config_get16(config_handle, DB_CONF_STATUS);
1685 	cr->arb_control = pci_config_get16(config_handle, DB_CONF_ARBITER_CTRL);
1686 	cr->p_serr_disables = pci_config_get8(config_handle,
1688 	cr->s_serr_disables = pci_config_get8(config_handle,
1690 	cr->config_csr = pci_config_get16(config_handle, DB_CONF_CONF_CSR);
1691 	cr->reset_control = pci_config_get32(config_handle, DB_CONF_RESET_CTRL);
1692 	cr->pm_cap = pci_config_get16(config_handle, DB_CONF_PM_CAP);
1693 	cr->pm_csr = pci_config_get16(config_handle, DB_CONF_PM_CSR);
1694 	cr->hs_csr = pci_config_get8(config_handle, DB_CONF_HS_CSR);
2253 	ddi_acc_handle_t config_handle;
2304 	    (pci_config_setup(child, &config_handle) != DDI_SUCCESS)) {
2312 	header_type = pci_config_get8(config_handle, PCI_CONF_HEADER);
2319 	command = pci_config_get16(config_handle, PCI_CONF_COMM);
2322 	pci_config_put16(config_handle, PCI_CONF_COMM, command);
2326 	    pci_config_get16(config_handle, PCI_CONF_VENID),
2327 	    pci_config_get16(config_handle, PCI_CONF_DEVID));
2333 		bcr = pci_config_get8(config_handle, PCI_BCNF_BCNTRL);
2339 		pci_config_put8(config_handle, PCI_BCNF_BCNTRL, bcr);
2351 		pci_config_put8(config_handle, PCI_CONF_CACHE_LINESZ,
2353 		n = pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ);
2371 			pci_config_put8(config_handle, PCI_BCNF_LATENCY_TIMER,
2374 			min_gnt = pci_config_get8(config_handle,
2378 		pci_config_put8(config_handle, PCI_CONF_LATENCY_TIMER,
2380 		n = pci_config_get8(config_handle, PCI_CONF_LATENCY_TIMER);
2389 	pci_config_teardown(&config_handle);
2449 	ddi_acc_handle_t config_handle;
2485 		if (pci_config_setup(dip, &config_handle) != DDI_SUCCESS) {
2497 		    pci_config_get16(config_handle, PCI_CONF_COMM);
2499 		    pci_config_get8(config_handle, PCI_CONF_HEADER);
2502 			    pci_config_get16(config_handle, PCI_BCNF_BCNTRL);
2504 		    pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ);
2506 		    pci_config_get8(config_handle, PCI_CONF_LATENCY_TIMER);
2509 			    pci_config_get8(config_handle,
2511 		pci_config_teardown(&config_handle);
2533 	ddi_acc_handle_t config_handle;
2545 		if (pci_config_setup(dip, &config_handle) != DDI_SUCCESS) {
2554 		pci_config_put16(config_handle, PCI_CONF_COMM, statep->command);
2556 			pci_config_put16(config_handle, PCI_BCNF_BCNTRL,
2558 		pci_config_put8(config_handle, PCI_CONF_CACHE_LINESZ,
2560 		pci_config_put8(config_handle, PCI_CONF_LATENCY_TIMER,
2563 			pci_config_put8(config_handle, PCI_BCNF_LATENCY_TIMER,
2565 		pci_config_teardown(&config_handle);