Lines Matching refs:unitp

226 	xcppm_unit_t *unitp;
230 unitp = ddi_get_soft_state(ppm_statep, ppm_inst);
240 &unitp->hndls.bbc_estar_ctrl);
242 unitp->regs.bbc_estar_ctrl = (uint16_t *)(base_addr +
244 unitp->regs.bbc_assert_change = (uint32_t *)(base_addr +
246 unitp->regs.bbc_pll_settle = (uint32_t *)(base_addr +
250 (caddr_t *)&unitp->regs.rio_mode_auxio,
251 0, 0, &attr_le, &unitp->hndls.rio_mode_auxio);
254 0, 0, &attr_le, &unitp->hndls.gpio_bank_select);
256 unitp->regs.gpio_bank_sel_index = (uint8_t *)(base_addr +
258 unitp->regs.gpio_bank_sel_data = (uint8_t *)(base_addr +
262 &unitp->hndls.gpio_data_ports);
264 unitp->regs.gpio_port1_data = (uint8_t *)(base_addr +
266 unitp->regs.gpio_port2_data = (uint8_t *)(base_addr +
272 ddi_regs_map_free(&unitp->hndls.bbc_estar_ctrl);
274 ddi_regs_map_free(&unitp->hndls.rio_mode_auxio);
276 ddi_regs_map_free(&unitp->hndls.gpio_bank_select);
278 ddi_regs_map_free(&unitp->hndls.gpio_data_ports);
286 XCPPM_SETGET8(unitp->hndls.gpio_bank_select,
287 unitp->regs.gpio_bank_sel_index, data8);
288 data8 = XCPPM_GET8(unitp->hndls.gpio_bank_select,
289 unitp->regs.gpio_bank_sel_data);
292 XCPPM_SETGET8(unitp->hndls.gpio_bank_select,
293 unitp->regs.gpio_bank_sel_data, data8);
305 xcppm_unit_t *unitp;
326 unitp = ddi_get_soft_state(ppm_statep, ppm_inst);
327 mutex_init(&unitp->unit_lock, NULL, MUTEX_DRIVER, NULL);
328 mutex_init(&unitp->creator_lock, NULL, MUTEX_DRIVER, NULL);
339 unitp->dip = dip;
363 unitp = ddi_get_soft_state(ppm_statep, ppm_inst);
364 mutex_enter(&unitp->unit_lock);
365 unitp->state &= ~XCPPM_ST_SUSPENDED;
366 mutex_exit(&unitp->unit_lock);
387 xcppm_unit_t *unitp;
394 unitp = ddi_get_soft_state(ppm_statep, ppm_inst);
395 reg = XCPPM_GET8(unitp->hndls.gpio_data_ports,
396 unitp->regs.gpio_port1_data);
401 XCPPM_SETGET8(unitp->hndls.gpio_data_ports,
402 unitp->regs.gpio_port1_data, reg);
409 xcppm_unit_t *unitp;
413 unitp = ddi_get_soft_state(ppm_statep, ppm_inst);
414 mutex_enter(&unitp->unit_lock);
415 if (unitp->led_tid == 0) {
416 mutex_exit(&unitp->unit_lock);
430 unitp->led_tid = timeout(xcppm_blink_led, (void *)(uintptr_t)new_action,
432 mutex_exit(&unitp->unit_lock);
439 xcppm_unit_t *unitp;
444 unitp = ddi_get_soft_state(ppm_statep, ppm_inst);
445 mutex_enter(&unitp->unit_lock);
446 tid = unitp->led_tid;
447 unitp->led_tid = 0;
448 mutex_exit(&unitp->unit_lock);
450 mutex_enter(&unitp->unit_lock);
452 mutex_exit(&unitp->unit_lock);
460 xcppm_unit_t *unitp;
462 unitp = ddi_get_soft_state(ppm_statep, ppm_inst);
470 mutex_enter(&unitp->unit_lock);
471 unitp->state |= XCPPM_ST_SUSPENDED;
472 mutex_exit(&unitp->unit_lock);
600 xcppm_unit_t *unitp;
604 unitp = ddi_get_soft_state(ppm_statep, ppm_inst);
605 mutex_enter(&unitp->gpio_lock);
607 data8 = buf8 = XCPPM_GET8(unitp->hndls.gpio_data_ports,
608 unitp->regs.gpio_port2_data);
623 XCPPM_SETGET8(unitp->hndls.gpio_data_ports,
624 unitp->regs.gpio_port2_data, data8);
637 mutex_exit(&unitp->gpio_lock);
738 xcppm_rio_mode(xcppm_unit_t *unitp, int mode)
742 mutex_enter(&unitp->gpio_lock);
743 data32 = buf32 = XCPPM_GET32(unitp->hndls.rio_mode_auxio,
744 unitp->regs.rio_mode_auxio);
749 XCPPM_SETGET32(unitp->hndls.rio_mode_auxio,
750 unitp->regs.rio_mode_auxio, data32);
751 mutex_exit(&unitp->gpio_lock);
774 xcppm_unit_t *unitp;
779 unitp = ddi_get_soft_state(ppm_statep, ppm_inst);
780 ASSERT(unitp);
822 xcppm_rio_mode(unitp, XCPPM_SETBIT);
854 xcppm_rio_mode(unitp, XCPPM_CLRBIT);
867 XCPPM_SETGET32(unitp->hndls.bbc_estar_ctrl,
868 (caddr_t)unitp->regs.bbc_assert_change, data32);
873 XCPPM_SETGET32(unitp->hndls.bbc_estar_ctrl,
874 (caddr_t)unitp->regs.bbc_pll_settle, data32);
879 XCPPM_SETGET16(unitp->hndls.bbc_estar_ctrl,
880 (caddr_t)unitp->regs.bbc_estar_ctrl, data16);
890 xcppm_rio_mode(unitp, XCPPM_CLRBIT);
1425 xcppm_unit_t *unitp;
1461 unitp = ddi_get_soft_state(ppm_statep, ppm_inst);
1462 mutex_enter(&unitp->unit_lock);
1463 if (unitp->state & XCPPM_ST_SUSPENDED) {
1464 mutex_exit(&unitp->unit_lock);
1469 unitp->led_tid = timeout(xcppm_blink_led,
1471 mutex_exit(&unitp->unit_lock);