Lines Matching refs:g5
324 ldxa [%g4]ASI_DMMU, %g5 /* rd old ctxnum */
325 srlx %g5, CTXREG_NEXT_SHIFT, %g2 /* %g2 = nucleus pgsz */
331 stxa %g5, [%g4]ASI_DMMU /* restore old ctxnum */
378 sethi %hi(FLUSH_ADDR), %g5
382 flush %g5 ! flush required by immu
395 SFMMU_CPU_CNUM(%g2, %g5, %g6) ! %g5 = sfmmu cnum on this CPU
401 or %g5, %g4, %g5
407 or %g5, %g2, %g5 /* %g5 = nucleus pgsz | primary pgsz | cnum */
408 stxa %g5, [%g4]ASI_DMMU /* wr new ctxum */
411 sethi %hi(FLUSH_ADDR), %g5
415 flush %g5 ! flush required by immu
500 DCACHE_FLUSHPAGE(%g1, %g2, %g3, %g4, %g5)
769 PN_L2_FLUSHALL(%g3, %g4, %g5)
1163 mov 1, %g5
1164 sll %g5, PIL_15, %g5
1165 wr %g5, CLEAR_SOFTINT
1336 * or not to unpark later. %g5 and %g4 are scratch registers.
1338 PARK_SIBLING_CORE(%g1, %g5, %g4)
1348 * %g5 = scr1
1356 DO_CPU_LOGOUT(%g3, %g2, %g6, %g4, %g5, %g6, %g3, %g4)
1363 PN_L2_FLUSHALL(%g4, %g5, %g6)
1365 CPU_INDEX(%g4, %g5)
1367 set cpunodes, %g5
1368 add %g4, %g5, %g4
1369 ld [%g4 + ECACHE_LINESIZE], %g5
1373 ECACHE_FLUSHALL(%g4, %g5, %g6, %g7)
1379 ASM_LD(%g5, dcache_size)
1381 CH_DCACHE_FLUSHALL(%g5, %g6, %g7)
1388 GET_CPU_PRIVATE_PTR(%g0, %g5, %g7, fast_ecc_err_5);
1389 ld [%g5 + CHPR_ICACHE_LINESIZE], %g6
1391 ld [%g5 + CHPR_ICACHE_SIZE], %g5
1393 ASM_LD(%g5, icache_size)
1396 CH_ICACHE_FLUSHALL(%g5, %g6, %g7, %g4)
1402 * whether or not we need to unpark. %g5 and %g4 are scratch registers.
1404 UNPARK_SIBLING_CORE(%g1, %g5, %g4)
1649 * or not to unpark later. %g5 and %g4 are scratch registers.
1651 PARK_SIBLING_CORE(%g1, %g5, %g4)
1661 * %g5 = scr1
1668 DO_CPU_LOGOUT(%g3, %g2, %g6, %g4, %g5, %g6, %g3, %g4)
1675 GET_CPU_PRIVATE_PTR(%g0, %g5, %g7, ce_err_1);
1676 ld [%g5 + CHPR_ICACHE_LINESIZE], %g6
1678 ld [%g5 + CHPR_ICACHE_SIZE], %g5
1680 ASM_LD(%g5, icache_size)
1683 CH_ICACHE_FLUSHALL(%g5, %g6, %g7, %g4)
1689 * whether or not we need to unpark. %g5 and %g4 are scratch registers.
1691 UNPARK_SIBLING_CORE(%g1, %g5, %g4)
1864 * %g5 = scr1
1869 andcc %g5, T_TL1, %g0
1873 sllx %g5, CLO_FLAGS_TT_SHIFT, %g4
1880 DO_CPU_LOGOUT(%g3, %g2, %g6, %g4, %g5, %g6, %g3, %g4)
1898 GET_CPU_PRIVATE_PTR(%g0, %g5, %g7, async_err_1);
1899 ld [%g5 + CHPR_ICACHE_LINESIZE], %g6
1901 ld [%g5 + CHPR_ICACHE_SIZE], %g5
1903 ASM_LD(%g5, icache_size)
1906 CH_ICACHE_FLUSHALL(%g5, %g6, %g7, %g4)
1916 ASM_LD(%g5, dcache_size)
1918 CH_DCACHE_FLUSHALL(%g5, %g6, %g7)
1924 * whether or not we need to unpark. %g5 and %g7 are scratch registers.
1926 UNPARK_SIBLING_CORE(%g1, %g5, %g7)
1965 RESET_USER_RTT_REGS(%g4, %g5, async_err_resetskip)
2081 CPU_INDEX(%g6, %g5)
2083 set trap_trace_ctl, %g5
2084 add %g6, %g5, %g6
2085 ld [%g6 + TRAPTR_LIMIT], %g5
2086 tst %g5
2089 ldx [%g6 + TRAPTR_PBASE], %g5
2091 add %g5, %g4, %g5
2099 stxa %g4, [%g5 + TRAP_ENT_TICK]%asi
2101 stha %g4, [%g5 + TRAP_ENT_TL]%asi
2103 stha %g4, [%g5 + TRAP_ENT_TT]%asi
2105 stna %g4, [%g5 + TRAP_ENT_TPC]%asi
2107 stxa %g4, [%g5 + TRAP_ENT_TSTATE]%asi
2108 stna %sp, [%g5 + TRAP_ENT_SP]%asi
2109 stna %g0, [%g5 + TRAP_ENT_TR]%asi
2110 stna %g0, [%g5 + TRAP_ENT_F1]%asi
2111 stna %g0, [%g5 + TRAP_ENT_F2]%asi
2112 stna %g0, [%g5 + TRAP_ENT_F3]%asi
2113 stna %g0, [%g5 + TRAP_ENT_F4]%asi
2119 ld [%g6 + TRAPTR_OFFSET], %g5
2121 st %g5, [%g6 + TRAPTR_LAST_OFFSET]
2122 add %g5, TRAP_ENT_SIZE, %g5
2124 cmp %g5, %g4
2125 movge %icc, 0, %g5
2126 st %g5, [%g6 + TRAPTR_OFFSET]
2262 CPU_INDEX(%g6, %g5)
2264 set trap_trace_ctl, %g5
2265 add %g6, %g5, %g6
2266 ld [%g6 + TRAPTR_LIMIT], %g5
2267 tst %g5
2270 ldx [%g6 + TRAPTR_PBASE], %g5
2272 add %g5, %g4, %g5
2280 stxa %g4, [%g5 + TRAP_ENT_TICK]%asi
2282 stha %g4, [%g5 + TRAP_ENT_TL]%asi
2284 stha %g4, [%g5 + TRAP_ENT_TT]%asi
2286 stna %g4, [%g5 + TRAP_ENT_TPC]%asi
2288 stxa %g4, [%g5 + TRAP_ENT_TSTATE]%asi
2289 stna %sp, [%g5 + TRAP_ENT_SP]%asi
2290 stna %g0, [%g5 + TRAP_ENT_TR]%asi
2291 stna %g0, [%g5 + TRAP_ENT_F1]%asi
2292 stna %g0, [%g5 + TRAP_ENT_F2]%asi
2293 stna %g0, [%g5 + TRAP_ENT_F3]%asi
2294 stna %g0, [%g5 + TRAP_ENT_F4]%asi
2300 ld [%g6 + TRAPTR_OFFSET], %g5
2302 st %g5, [%g6 + TRAPTR_LAST_OFFSET]
2303 add %g5, TRAP_ENT_SIZE, %g5
2305 cmp %g5, %g4
2306 movge %icc, 0, %g5
2307 st %g5, [%g6 + TRAPTR_OFFSET]
2774 ! %g2, %g3, %g5 - scratch
2782 GET_CPU_PRIVATE_PTR(%g2, %g4, %g5, 1f);