Lines Matching refs:g4
319 ldub [%g2 + SFMMU_CEXT], %g4 ! %g4 = sfmmup->cext
320 sll %g4, CTXREG_EXT_SHIFT, %g4
321 or %g6, %g4, %g6 ! %g6 = pgsz | cnum
323 set MMU_PCONTEXT, %g4
324 ldxa [%g4]ASI_DMMU, %g5 /* rd old ctxnum */
328 stxa %g6, [%g4]ASI_DMMU /* wr new ctxum */
331 stxa %g5, [%g4]ASI_DMMU /* restore old ctxnum */
362 set SFMMU_PGCNT_MASK, %g4
363 and %g4, %g2, %g3 /* g3 = pgcnt - 1 */
369 sethi %hi(ksfmmup), %g4
370 ldx [%g4 + %lo(ksfmmup)], %g4
371 cmp %g4, %g2
399 ldub [%g2 + SFMMU_CEXT], %g4 ! %g4 = sfmmup->cext
400 sll %g4, CTXREG_EXT_SHIFT, %g4
401 or %g5, %g4, %g5
403 set MMU_PCONTEXT, %g4
404 ldxa [%g4]ASI_DMMU, %g6 /* rd old ctxnum */
408 stxa %g5, [%g4]ASI_DMMU /* wr new ctxum */
421 stxa %g6, [%g4]ASI_DMMU /* restore old ctxnum */
440 set DEMAP_ALL_TYPE, %g4
441 stxa %g0, [%g4]ASI_DTLB_DEMAP
442 stxa %g0, [%g4]ASI_ITLB_DEMAP
500 DCACHE_FLUSHPAGE(%g1, %g2, %g3, %g4, %g5)
544 DCACHE_FLUSHCOLOR(%g1, 0, %g2, %g3, %g4)
545 DCACHE_FLUSHCOLOR(%g1, 1, %g2, %g3, %g4)
546 DCACHE_FLUSHCOLOR(%g1, 2, %g2, %g3, %g4)
547 DCACHE_FLUSHCOLOR(%g1, 3, %g2, %g3, %g4)
769 PN_L2_FLUSHALL(%g3, %g4, %g5)
1149 CPU_INDEX(%g1, %g4)
1150 set ch_err_tl1_pending, %g4
1151 ldub [%g1 + %g4], %g2
1158 stb %g0, [%g1 + %g4]
1175 mov PIL_15, %g4
1185 mov PIL_15, %g4
1296 andn %g1, DCU_DC + DCU_IC, %g4
1297 stxa %g4, [%g0]ASI_DCU
1300 ASM_JMP(%g4, fast_ecc_err)
1324 andn %g3, EN_REG_NCEEN + EN_REG_CEEN, %g4
1325 stxa %g4, [%g0]ASI_ESTATE_ERR
1336 * or not to unpark later. %g5 and %g4 are scratch registers.
1338 PARK_SIBLING_CORE(%g1, %g5, %g4)
1344 * into this macro via %g4. Output only valid if cpu_private
1347 * %g4 = Trap information stored in the cpu logout flags field
1351 * %g4 = scr4
1354 and %g3, EN_REG_CEEN + EN_REG_NCEEN, %g4
1356 DO_CPU_LOGOUT(%g3, %g2, %g6, %g4, %g5, %g6, %g3, %g4)
1363 PN_L2_FLUSHALL(%g4, %g5, %g6)
1365 CPU_INDEX(%g4, %g5)
1366 mulx %g4, CPU_NODE_SIZE, %g4
1368 add %g4, %g5, %g4
1369 ld [%g4 + ECACHE_LINESIZE], %g5
1370 ld [%g4 + ECACHE_SIZE], %g4
1373 ECACHE_FLUSHALL(%g4, %g5, %g6, %g7)
1396 CH_ICACHE_FLUSHALL(%g5, %g6, %g7, %g4)
1402 * whether or not we need to unpark. %g5 and %g4 are scratch registers.
1404 UNPARK_SIBLING_CORE(%g1, %g5, %g4)
1448 rdpr %pil, %g4
1449 cmp %g4, PIL_14
1451 movl %icc, PIL_14, %g4
1637 andn %g1, DCU_IC, %g4
1638 stxa %g4, [%g0]ASI_DCU
1649 * or not to unpark later. %g5 and %g4 are scratch registers.
1651 PARK_SIBLING_CORE(%g1, %g5, %g4)
1657 * into this macro via %g4. Output only valid if cpu_private
1660 * %g4 = Trap information stored in the cpu logout flags field
1664 * %g4 = scr4
1666 clr %g4 ! TL=0 bit in afsr
1668 DO_CPU_LOGOUT(%g3, %g2, %g6, %g4, %g5, %g6, %g3, %g4)
1683 CH_ICACHE_FLUSHALL(%g5, %g6, %g7, %g4)
1689 * whether or not we need to unpark. %g5 and %g4 are scratch registers.
1691 UNPARK_SIBLING_CORE(%g1, %g5, %g4)
1735 rdpr %pil, %g4
1736 cmp %g4, PIL_14
1738 movl %icc, PIL_14, %g4
1826 andn %g3, EN_REG_NCEEN + EN_REG_CEEN, %g4
1827 stxa %g4, [%g0]ASI_ESTATE_ERR
1839 andn %g1, DCU_IC + DCU_DC, %g4
1840 stxa %g4, [%g0]ASI_DCU
1851 * or not to unpark later. %g6 and %g4 are scratch registers.
1853 PARK_SIBLING_CORE(%g1, %g6, %g4)
1860 * into this macro via %g4. Output only valid if cpu_private
1863 * %g4 = Trap information stored in the cpu logout flags field
1867 * %g4 = scr4
1873 sllx %g5, CLO_FLAGS_TT_SHIFT, %g4
1875 and %g4, %g2, %g4 ! ttype
1876 or %g6, %g4, %g4 ! TT and TL
1878 or %g3, %g4, %g4 ! TT and TL and CEEN
1880 DO_CPU_LOGOUT(%g3, %g2, %g6, %g4, %g5, %g6, %g3, %g4)
1890 sllx %g4, 32, %g4
1891 or %g4, %g3, %g3
1906 CH_ICACHE_FLUSHALL(%g5, %g6, %g7, %g4)
1965 RESET_USER_RTT_REGS(%g4, %g5, async_err_resetskip)
1969 mov PIL_15, %g4 ! run at pil 15
1998 mov PIL_15, %g4 ! run at pil 15
2090 ld [%g6 + TRAPTR_OFFSET], %g4
2091 add %g5, %g4, %g5
2098 rd STICK, %g4
2099 stxa %g4, [%g5 + TRAP_ENT_TICK]%asi
2100 rdpr %tl, %g4
2101 stha %g4, [%g5 + TRAP_ENT_TL]%asi
2102 rdpr %tt, %g4
2103 stha %g4, [%g5 + TRAP_ENT_TT]%asi
2104 rdpr %tpc, %g4
2105 stna %g4, [%g5 + TRAP_ENT_TPC]%asi
2106 rdpr %tstate, %g4
2107 stxa %g4, [%g5 + TRAP_ENT_TSTATE]%asi
2120 ld [%g6 + TRAPTR_LIMIT], %g4
2123 sub %g4, TRAP_ENT_SIZE, %g4
2124 cmp %g5, %g4
2140 mov 1, %g4
2141 sllx %g4, DCU_PE_SHIFT, %g4
2142 andn %g3, %g4, %g3
2180 mov PIL_15, %g4 ! run at pil 15
2271 ld [%g6 + TRAPTR_OFFSET], %g4
2272 add %g5, %g4, %g5
2279 rd STICK, %g4
2280 stxa %g4, [%g5 + TRAP_ENT_TICK]%asi
2281 rdpr %tl, %g4
2282 stha %g4, [%g5 + TRAP_ENT_TL]%asi
2283 rdpr %tt, %g4
2284 stha %g4, [%g5 + TRAP_ENT_TT]%asi
2285 rdpr %tpc, %g4
2286 stna %g4, [%g5 + TRAP_ENT_TPC]%asi
2287 rdpr %tstate, %g4
2288 stxa %g4, [%g5 + TRAP_ENT_TSTATE]%asi
2301 ld [%g6 + TRAPTR_LIMIT], %g4
2304 sub %g4, TRAP_ENT_SIZE, %g4
2305 cmp %g5, %g4
2461 jmp %g4 + 4
2597 rd STICK, %g4 ! read stick reg
2598 add %g4, %o0, %o1 ! adjust stick with skew
2775 ! %g4 - ptr. to scrub_misc chsm_outstanding[index].
2782 GET_CPU_PRIVATE_PTR(%g2, %g4, %g5, 1f);
2783 ld [%g4], %g2 ! cpu's chsm_outstanding[index]
2790 st %g3, [%g4] ! delay - store incremented counter
3182 set MMU_TAG_ACCESS, %g4
3183 stxa %o2, [%g4]ASI_IMMU
3251 set MMU_TAG_ACCESS, %g4
3252 stxa %o2, [%g4]ASI_DMMU