Lines Matching defs:as
589 * system clock rate as the basis for low level timing,
648 int proc_as; /* null as */
669 * Attempt to recover a cpu by claiming every cache line as saved
684 struct as *as;
721 if ((as = p->p_as) == NULL) {
726 if ((hat = as->a_hat) == NULL) {
751 /* Verify as */
752 if (hat->sfmmu_as != as) {
1484 * be logged as part of the panic flow.
1718 * be logged as part of the panic flow.
2040 * be logged as part of the panic flow.
2075 * are also detected (reported as TT 0x71) and handled by this trap
2134 * then process as a true ddspe. A true
2233 * As far as clearing P$ parity errors, it is enough to
2262 * be logged as part of the panic flow.
2501 * We want to skip logging in the same conditions as the
2527 * break and handle as if falling through from a UE; if not,
2761 * notification as to make little real forward progress.
2765 * if the offending address has just been unconfigured as part of
2784 * marked the fault structure as incomplete as a flag to later
2791 * short time, and cpu_ce_delayed_ec_logout will mark it as busy in
2895 * of SSM mode with Owner as victimisation of such
2976 * Restrict choice to active cpus in the same cpu partition as ourselves in
2983 * We prefer a partner that is in a different latency group to ourselves as
3022 * in the detector's partition is on the same chip as the detector
3055 * . is still in the same partition as the detector
3135 * If locptnr is not NULL it is a cpu in the same lgroup as the
3214 * delayed actions as required. Note that we are no longer necessarily running
3257 * Some correctable events are not scrubbed/classified, such as those
3523 * so it will interpret this as a memory error.
3738 * during initial classification (it is valid if we're called as part of
3745 * we should count such occurences. Anyway, for now, we'll leave it as
3801 * physical address range twice as large as the Ecache.
4149 * Panther has twice as many instructions per icache line and the
4788 * same class as the t_afsr_bit are also C_AFSR_MEMORY bits.
4995 * below, but the sdw_addr and sdw_stat will stay as the
5006 * If the primary and shadow AFSR differ, tag the shadow as
5015 * Check AFSR bits as well as AFSR_EXT bits in order of
6031 * become negative after the atomic_add_32_nv(). This is not a problem, as
6155 * overhead as the cost of correctness in the case where we get
6187 * - invoking as target of an x-call in which case we're at XCALL_PIL
6241 * scrub as a result of a CE being triggered by
6261 * This is a slow way to do a scrub, but as it will
6266 * cut down what we need to check as the scrubber
6290 * as a CE noticed with CEEN off. It is assumed that we are still running
6410 * FRC: Can't scrub memory as we don't have AFAR for Jalapeno.
6413 * be properly classified as intermittent, persistent, etc.
6416 * Must scrub memory before cpu_queue_events, as scrubbing memory sets
6427 * Must scrub memory before cpu_queue_events, as scrubbing memory sets
6504 * flush the cache line affected as the ME bit
7048 * take appropriate further action (such as a reboot, contract