Lines Matching refs:g6
192 DO_TL1_CPU_LOGOUT(%g3, %g2, %g4, %g5, %g6, %g3, %g4)
221 GET_CPU_IMPL(%g6)
222 cmp %g6, PANTHER_IMPL
227 mov %g6, %g3
249 CH_DCACHE_FLUSHALL(%g4, %g5, %g6)
272 GET_CPU_IMPL(%g6)
276 cmp %g6, PANTHER_IMPL
279 CH_ICACHE_FLUSHALL(%g4, %g5, %g6, %g3)
294 CPU_INDEX(%g6, %g5)
295 sll %g6, TRAPTR_SIZE_SHIFT, %g6
297 add %g6, %g5, %g6
298 ld [%g6 + TRAPTR_LIMIT], %g5
302 ldx [%g6 + TRAPTR_PBASE], %g5
303 ld [%g6 + TRAPTR_OFFSET], %g4
340 ld [%g6 + TRAPTR_OFFSET], %g5
341 ld [%g6 + TRAPTR_LIMIT], %g4
342 st %g5, [%g6 + TRAPTR_LAST_OFFSET]
347 st %g5, [%g6 + TRAPTR_OFFSET]
372 GET_CPU_IMPL(%g6)
373 cmp %g6, PANTHER_IMPL
389 GET_CPU_IMPL(%g6)
390 cmp %g6, PANTHER_IMPL
394 set ASI_AFSR_EXT_VA, %g6 ! ASI of current AFSR_EXT
395 ldxa [%g6]ASI_AFSR, %g3 ! value of current AFSR_EXT
680 set CHPR_TLB_LOGOUT, %g6
681 GET_CPU_PRIVATE_PTR(%g6, %g1, %g5, itlb_parity_trap_1)
682 set LOGOUT_INVALID_U32, %g6
683 sllx %g6, 32, %g6 ! if our logout structure is
685 or %g5, %g6, %g5 ! already being used, then we
686 ldx [%g1 + PN_TLO_ADDR], %g6 ! don't collect any diagnostic
687 cmp %g6, %g5 ! information before clearing
707 set PN_TLB_ACC_WAY_BIT, %g6 ! same thing again for way 1
708 or %g4, %g6, %g4
716 andn %g4, %g6, %g4 ! back to way 0
733 set PN_TLB_ACC_WAY_BIT, %g6 ! same thing again for way 1
734 or %g4, %g6, %g4
739 sethi %hi(FLUSH_ADDR), %g6 ! PRM says we need to issue a
740 flush %g6 ! flush after writing MMU regs
843 rdpr %tl, %g6 ! read current trap level
844 cmp %g6, 1 ! skip over the tl>1 code
853 mov 1, %g6
854 sllx %g6, PN_TLO_INFO_TL1_SHIFT, %g6
855 or %g6, %g3, %g3
871 set CHPR_TLB_LOGOUT, %g6
872 GET_CPU_PRIVATE_PTR(%g6, %g1, %g5, dtlb_parity_trap_2)
873 set LOGOUT_INVALID_U32, %g6
874 sllx %g6, 32, %g6 ! if our logout structure is
876 or %g5, %g6, %g5 ! already being used, then we
877 ldx [%g1 + PN_TLO_ADDR], %g6 ! don't collect any diagnostic
878 cmp %g6, %g5 ! information before clearing
906 set PN_TLB_ACC_WAY_BIT, %g6 ! same thing again for way 1
907 or %g4, %g6, %g4 ! of each TLB.
908 or %g7, %g6, %g7
921 andn %g4, %g6, %g4 ! back to way 0
922 andn %g7, %g6, %g7 ! back to way 0
942 set PN_TLB_ACC_WAY_BIT, %g6 ! same thing again for way 1
943 or %g4, %g6, %g4
944 or %g7, %g6, %g7
950 sethi %hi(FLUSH_ADDR), %g6 ! PRM says we need to issue a
951 flush %g6 ! flush after writing MMU regs