Lines Matching refs:g5
185 * current CEEN state, %g5 must point to logout structure in
191 add %g1, CH_ERR_TL1_LOGOUT, %g5
192 DO_TL1_CPU_LOGOUT(%g3, %g2, %g4, %g5, %g6, %g3, %g4)
207 andn %g7, EN_REG_CEEN | EN_REG_NCEEN, %g5
208 stxa %g5, [%g0]ASI_ESTATE_ERR
216 PN_L2_FLUSHALL(%g3, %g4, %g5)
219 set CH_ECACHE_MIN_LSIZE, %g5
228 CHP_ECACHE_FLUSHALL(%g4, %g5, %g3)
248 ASM_LD(%g5, dcache_linesize)
249 CH_DCACHE_FLUSHALL(%g4, %g5, %g6)
275 mov CH_ICACHE_LSIZE, %g5
278 movz %xcc, PN_ICACHE_LSIZE, %g5
279 CH_ICACHE_FLUSHALL(%g4, %g5, %g6, %g3)
294 CPU_INDEX(%g6, %g5)
296 set trap_trace_ctl, %g5
297 add %g6, %g5, %g6
298 ld [%g6 + TRAPTR_LIMIT], %g5
299 tst %g5
302 ldx [%g6 + TRAPTR_PBASE], %g5
304 add %g5, %g4, %g5
312 stxa %g4, [%g5 + TRAP_ENT_TICK]%asi
314 stha %g4, [%g5 + TRAP_ENT_TL]%asi
316 stha %g4, [%g5 + TRAP_ENT_TT]%asi
318 stna %g4, [%g5 + TRAP_ENT_TPC]%asi
320 stxa %g4, [%g5 + TRAP_ENT_TSTATE]%asi
321 stna %sp, [%g5 + TRAP_ENT_SP]%asi
322 stna %g0, [%g5 + TRAP_ENT_TR]%asi
327 stna %g3, [%g5 + TRAP_ENT_F1]%asi
328 stna %g4, [%g5 + TRAP_ENT_F2]%asi
333 stna %g3, [%g5 + TRAP_ENT_F3]%asi
334 stna %g4, [%g5 + TRAP_ENT_F4]%asi
340 ld [%g6 + TRAPTR_OFFSET], %g5
342 st %g5, [%g6 + TRAPTR_LAST_OFFSET]
343 add %g5, TRAP_ENT_SIZE, %g5
345 cmp %g5, %g4
346 movge %icc, 0, %g5
347 st %g5, [%g6 + TRAPTR_OFFSET]
646 set TAGREAD_CTX_MASK, %g5
647 and %g4, %g5, %g4
663 set PN_ITLB_PGSZ_MASK, %g5
664 and %g3, %g5, %g5
665 srlx %g5, PN_ITLB_PGSZ_SHIFT, %g5
666 PN_GET_TLB_INDEX(%g4, %g5) ! %g4 has the index
668 set PN_ITLB_T512, %g5
669 or %g4, %g5, %g4 ! and add in the TLB ID
681 GET_CPU_PRIVATE_PTR(%g6, %g1, %g5, itlb_parity_trap_1)
684 set LOGOUT_INVALID_L32, %g5 ! unavailable or if it is
685 or %g5, %g6, %g5 ! already being used, then we
687 cmp %g6, %g5 ! information before clearing
702 ldxa [%g4]ASI_ITLB_ACCESS, %g5 ! read the data
703 stx %g5, [%g1 + CH_TLO_TTE_DATA] ! store it away
704 ldxa [%g4]ASI_ITLB_TAGREAD, %g5 ! read the tag
705 stx %g5, [%g1 + CH_TLO_TTE_TAG] ! store it away
711 ldxa [%g4]ASI_ITLB_ACCESS, %g5 ! read the data
712 stx %g5, [%g1 + CH_TLO_TTE_DATA] ! store it away
713 ldxa [%g4]ASI_ITLB_TAGREAD, %g5 ! read the tag
714 stx %g5, [%g1 + CH_TLO_TTE_TAG] ! store it away
728 set MMU_TAG_ACCESS, %g5 ! We write a TTE tag value of
729 stxa %g0, [%g5]ASI_IMMU ! 0 as it will be invalid.
797 set TAGREAD_CTX_MASK, %g5 ! 'or' in the trap context
798 and %g4, %g5, %g4 ! to complete the tlo_info
813 set PN_DTLB_PGSZ0_MASK, %g5
814 and %g3, %g5, %g5
815 srlx %g5, PN_DTLB_PGSZ0_SHIFT, %g5
816 PN_GET_TLB_INDEX(%g4, %g5) ! %g4 has the DTLB_0 index
818 set PN_DTLB_T512_0, %g5
819 or %g4, %g5, %g4 ! and add in the TLB ID
822 set PN_DTLB_PGSZ1_MASK, %g5
823 and %g3, %g5, %g5
824 srlx %g5, PN_DTLB_PGSZ1_SHIFT, %g5
825 PN_GET_TLB_INDEX(%g7, %g5) ! %g7 has the DTLB_1 index
827 set PN_DTLB_T512_1, %g5
828 or %g7, %g5, %g7 ! and add in the TLB ID
872 GET_CPU_PRIVATE_PTR(%g6, %g1, %g5, dtlb_parity_trap_2)
875 set LOGOUT_INVALID_L32, %g5 ! unavailable or if it is
876 or %g5, %g6, %g5 ! already being used, then we
878 cmp %g6, %g5 ! information before clearing
891 rdpr %tpc, %g5
892 stx %g5, [%g1 + PN_TLO_PC]
896 ldxa [%g4]ASI_DTLB_ACCESS, %g5 ! read the data from DTLB_0
897 stx %g5, [%g1 + CH_TLO_TTE_DATA] ! way 0 and store it away
898 ldxa [%g4]ASI_DTLB_TAGREAD, %g5 ! read the tag from DTLB_0
899 stx %g5, [%g1 + CH_TLO_TTE_TAG] ! way 0 and store it away
901 ldxa [%g7]ASI_DTLB_ACCESS, %g5 ! now repeat for DTLB_1 way 0
902 stx %g5, [%g1 + (CH_TLO_TTE_DATA + (CH_TLO_TTE_SIZE * 2))]
903 ldxa [%g7]ASI_DTLB_TAGREAD, %g5
904 stx %g5, [%g1 + (CH_TLO_TTE_TAG + (CH_TLO_TTE_SIZE * 2))]
911 ldxa [%g4]ASI_DTLB_ACCESS, %g5 ! read the data from DTLB_0
912 stx %g5, [%g1 + CH_TLO_TTE_DATA] ! way 1 and store it away
913 ldxa [%g4]ASI_DTLB_TAGREAD, %g5 ! read the tag from DTLB_0
914 stx %g5, [%g1 + CH_TLO_TTE_TAG] ! way 1 and store it away
916 ldxa [%g7]ASI_DTLB_ACCESS, %g5 ! now repeat for DTLB_1 way 1
917 stx %g5, [%g1 + (CH_TLO_TTE_DATA + (CH_TLO_TTE_SIZE * 2))]
918 ldxa [%g7]ASI_DTLB_TAGREAD, %g5
919 stx %g5, [%g1 + (CH_TLO_TTE_TAG + (CH_TLO_TTE_SIZE * 2))]
936 set MMU_TAG_ACCESS, %g5 ! We write a TTE tag value of
937 stxa %g0, [%g5]ASI_DMMU ! 0 as it will be invalid.