Lines Matching refs:g1
155 * this routine with %g1 and %g2 already saved in %tpc, %tnpc and %tstate.
176 * the %tpc in ch_err_tl1_tpc. At the end of this macro, %g1 will
178 * will be saved in ch_err_tl1_tmp. All %g registers except for %g1
191 add %g1, CH_ERR_TL1_LOGOUT, %g5
239 ldxa [%g1 + CH_ERR_TL1_TMP]%asi, %g3
262 ldxa [%g1 + CH_ERR_TL1_TMP]%asi, %g3
324 ldxa [%g1 + CH_ERR_TL1_SDW_AFAR]%asi, %g3
325 ldxa [%g1 + CH_ERR_TL1_SDW_AFSR]%asi, %g4
330 ldxa [%g1 + CH_ERR_TL1_AFAR]%asi, %g3
331 ldxa [%g1 + CH_ERR_TL1_AFSR]%asi, %g4
355 ldxa [%g1 + CH_ERR_TL1_NEST_CNT]%asi, %g2
366 ldxa [%g1 + CH_ERR_TL1_SDW_AFSR]%asi, %g3
376 ldxa [%g1 + CH_ERR_TL1_SDW_AFSR_EXT]%asi, %g3
381 ldxa [%g1 + CH_ERR_TL1_AFSR]%asi, %g4 ! original AFSR
393 ldxa [%g1 + CH_ERR_TL1_SDW_AFSR_EXT]%asi, %g4 ! original AFSR_EXT
404 * it up and log it. %g1 must point to the ch_err_tl1_data structure.
508 andn %o0, (CH_ECACHE_SUBBLK_SIZE - 1), %g1
513 ldxa [%g1 + %o2]ASI_MEM, %g2
515 stxa %g2, [%g1 + %o2]ASI_MEM
518 setx 0xbadecc00badecc01, %g1, %g2
520 mov 8, %g1
521 stxa %g2, [%o0 + %g1]ASI_MEM
527 PN_ECACHE_FLUSH_LINE(%o0, %o1, %o2, %o3, %g1)
681 GET_CPU_PRIVATE_PTR(%g6, %g1, %g5, itlb_parity_trap_1)
686 ldx [%g1 + PN_TLO_ADDR], %g6 ! don't collect any diagnostic
693 * for use in ASI_ITLB_ACCESS and ASI_ITLB_TAGREAD. %g1 contains
696 stx %g3, [%g1 + PN_TLO_INFO]
697 stx %g2, [%g1 + PN_TLO_ADDR]
698 stx %g2, [%g1 + PN_TLO_PC] ! %tpc == fault addr for IMMU
700 add %g1, PN_TLO_ITLB_TTE, %g1 ! move up the pointer
703 stx %g5, [%g1 + CH_TLO_TTE_DATA] ! store it away
705 stx %g5, [%g1 + CH_TLO_TTE_TAG] ! store it away
709 add %g1, CH_TLO_TTE_SIZE, %g1 ! move up the pointer
712 stx %g5, [%g1 + CH_TLO_TTE_DATA] ! store it away
714 stx %g5, [%g1 + CH_TLO_TTE_TAG] ! store it away
749 set cpu_tlb_parity_error, %g1
872 GET_CPU_PRIVATE_PTR(%g6, %g1, %g5, dtlb_parity_trap_2)
877 ldx [%g1 + PN_TLO_ADDR], %g6 ! don't collect any diagnostic
886 * ASI_DTLB_TAGREAD. %g1 contains the pointer to our logout
889 stx %g3, [%g1 + PN_TLO_INFO]
890 stx %g2, [%g1 + PN_TLO_ADDR]
892 stx %g5, [%g1 + PN_TLO_PC]
894 add %g1, PN_TLO_DTLB_TTE, %g1 ! move up the pointer
897 stx %g5, [%g1 + CH_TLO_TTE_DATA] ! way 0 and store it away
899 stx %g5, [%g1 + CH_TLO_TTE_TAG] ! way 0 and store it away
902 stx %g5, [%g1 + (CH_TLO_TTE_DATA + (CH_TLO_TTE_SIZE * 2))]
904 stx %g5, [%g1 + (CH_TLO_TTE_TAG + (CH_TLO_TTE_SIZE * 2))]
909 add %g1, CH_TLO_TTE_SIZE, %g1 ! move up the pointer
912 stx %g5, [%g1 + CH_TLO_TTE_DATA] ! way 1 and store it away
914 stx %g5, [%g1 + CH_TLO_TTE_TAG] ! way 1 and store it away
917 stx %g5, [%g1 + (CH_TLO_TTE_DATA + (CH_TLO_TTE_SIZE * 2))]
919 stx %g5, [%g1 + (CH_TLO_TTE_TAG + (CH_TLO_TTE_SIZE * 2))]
962 set cpu_tlb_parity_error, %g1