Lines Matching refs:and
5 * Common Development and Distribution License (the "License").
11 * and limitations under the License.
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
82 and physaddr, scr1, scr1; \
90 * Panther version to reflush a line from both the L2 cache and L3
125 * to physaddr from both the L2 cache and the L3 cache.
140 and physaddr, l2_idx_out, l3_idx_out; \
145 and physaddr, l2_idx_out, l2_idx_out; \
155 * this routine with %g1 and %g2 already saved in %tpc, %tnpc and %tstate.
173 * This macro turns off the D$/I$ if they are on and saves their
175 * ch_err_tl1_data structure, updates the ch_err_tl1_flags and saves
177 * point to the ch_err_tl1_data structure and the original D$/I$ state
190 and %g4, EN_REG_CEEN, %g4
203 * Save the current CEEN and NCEEN state in %g7 and turn them off
231 * Restore CEEN and NCEEN to the previous state.
237 * If we turned off the D$, then flush it and turn it back on.
260 * If we turned off the I$, then flush it and turn it back on.
268 * Flush the I$. Panther has different I$ parameters, and we
353 * handling and just do the necessary cache-flushing.
361 * and panic since a UE will occur (on the retry) before the
362 * UCU and WDU messages are enqueued. On a Panther processor,
398 bnz %xcc, fecc_tl1_err ! panic (saw L3_WDU and UCU or L3_UCU)
403 * the ch_err_tl1_data structure and want the PIL15 softint to pick
404 * it up and log it. %g1 must point to the ch_err_tl1_data structure.
405 * Restores the %g registers and issues retry.
484 * in an entire ecache subblock's worth of data, and write it back out.
546 /* return and re-enable IE and AM */
559 * L2 cache and L3 cache.
611 * error is detected and we are running on Panther.
613 * In this routine we collect diagnostic information and write it to our
614 * logout structure (if possible) and clear all ITLB entries that may have
617 * and log any error messages. As for parameters to cpu_tlb_parity_error, we
644 and %g3, %g4, %g3
647 and %g4, %g5, %g4
648 or %g4, %g3, %g3 ! 'or' in the trap context and
664 and %g3, %g5, %g5
669 or %g4, %g5, %g4 ! and add in the TLB ID
688 bne itlb_parity_trap_1 ! and logging the error.
693 * for use in ASI_ITLB_ACCESS and ASI_ITLB_TAGREAD. %g1 contains
730 stxa %g0, [%g4]ASI_ITLB_ACCESS ! Write the data and tag
736 stxa %g0, [%g4]ASI_ITLB_ACCESS ! Write same data and tag
762 * error is detected and we are running on Panther.
764 * In this routine we collect diagnostic information and write it to our
765 * logout structure (if possible) and clear all DTLB entries that may have
768 * and log any error messages. As for parameters to cpu_tlb_parity_error, we
795 and %g3, %g4, %g3
798 and %g4, %g5, %g4 ! to complete the tlo_info
814 and %g3, %g5, %g5
819 or %g4, %g5, %g4 ! and add in the TLB ID
823 and %g3, %g5, %g5
828 or %g7, %g5, %g7 ! and add in the TLB ID
850 * update our tlo_info field and then skip to the TLB flush
879 bne dtlb_parity_trap_2 ! and logging the error.
884 * index + TLB ID and %g7 contains our DTLB_1 index + TLB ID
885 * both of which will be used for ASI_DTLB_ACCESS and
897 stx %g5, [%g1 + CH_TLO_TTE_DATA] ! way 0 and store it away
899 stx %g5, [%g1 + CH_TLO_TTE_TAG] ! way 0 and store it away
912 stx %g5, [%g1 + CH_TLO_TTE_DATA] ! way 1 and store it away
914 stx %g5, [%g1 + CH_TLO_TTE_TAG] ! way 1 and store it away
938 stxa %g0, [%g4]ASI_DTLB_ACCESS ! Write the data and tag.
946 stxa %g0, [%g4]ASI_DTLB_ACCESS ! Write same data and tag.
975 * Calculates the Panther TLB index based on a virtual address and page size