Lines Matching refs:tmp2
54 #define DCACHE_FLUSHPAGE(arg1, arg2, tmp1, tmp2, tmp3) \
60 sethi %hi(dflush_type), tmp2 ;\
61 ld [tmp2 + %lo(dflush_type)], tmp2 ;\
62 cmp tmp2, FLUSHPAGE_TYPE ;\
67 cmp tmp2, FLUSHMATCH_TYPE ;\
75 sub tmp3, tmp1, tmp2 ;\
77 stxa %g0, [tmp2]ASI_DC_TAG ;\
79 cmp %g0, tmp2 ;\
81 sub tmp2, tmp1, tmp2 ;\
89 * tmp2 = tag from cache \
97 ldxa [arg2 + tmp3]ASI_DC_TAG, tmp2 /* read tag */ ;\
98 btst SF_DC_VBIT_MASK, tmp2 ;\
100 andn tmp2, SF_DC_VBIT_MASK, tmp2 /* clear out v bits */ ;\
101 cmp tmp2, arg1 ;\
118 * tmp2 = cache tag \
123 ldxa [arg2]ASI_DC_TAG, tmp2 /* read tag */ ;\
124 btst SF_DC_VBIT_MASK, tmp2 ;\
126 andn tmp2, SF_DC_VBIT_MASK, tmp2 /* clear out v bits */ ;\
127 cmp tmp2, arg1 ;\
141 #define DCACHE_FLUSHCOLOR(arg, tmp1, tmp2) \
147 set MMU_PAGESIZE, tmp2; \
150 * tmp2 = page size \
154 sub tmp2, tmp1, tmp2; \
156 stxa %g0, [arg + tmp2]ASI_DC_TAG; \
158 cmp %g0, tmp2; \
160 sub tmp2, tmp1, tmp2; \
198 #define SF_WORKAROUND(tmp1, tmp2) \
199 sethi %hi(FLUSH_ADDR), tmp2 ;\
202 flush tmp2 ;
204 #define SF_WORKAROUND(tmp1, tmp2)
215 #define VTAG_FLUSHUPAGE(lbl, arg1, arg2, tmp1, tmp2, tmp3, tmp4) \
217 andn tmp1, PSTATE_IE, tmp2 ;\
218 wrpr tmp2, 0, %pstate ;\
219 sethi %hi(FLUSH_ADDR), tmp2 ;\
230 flush tmp2 ;\
234 flush tmp2 ;\
247 #define DTLB_FLUSH_UNLOCKED_UCTXS(lbl, arg1, tmp1, tmp2, tmp3, \
251 SF_WORKAROUND(tmp1, tmp2) ;\
261 ldxa [tmp3]ASI_DTLB_TAGREAD, tmp2 ;\
262 and tmp2, tmp1, tmp6 ;\
263 andn tmp2, tmp1, tmp5 ;\
268 VTAG_FLUSHUPAGE(VD/**/lbl, tmp5, tmp6, tmp1, tmp2, tmp3, tmp4) ;\
282 #define ITLB_FLUSH_UNLOCKED_UCTXS(lbl, arg1, tmp1, tmp2, tmp3, \
286 SF_WORKAROUND(tmp1, tmp2) ;\
296 ldxa [tmp3]ASI_ITLB_TAGREAD, tmp2 ;\
297 and tmp2, tmp1, tmp6 ;\
298 andn tmp2, tmp1, tmp5 ;\
303 VTAG_FLUSHUPAGE(VI/**/lbl, tmp5, tmp6, tmp1, tmp2, tmp3, tmp4) ;\