Lines Matching refs:tmp1
54 #define DCACHE_FLUSHPAGE(arg1, arg2, tmp1, tmp2, tmp3) \
55 ldxa [%g0]ASI_LSU, tmp1 ;\
56 btst LSU_DC, tmp1 /* is dcache enabled? */ ;\
58 sethi %hi(dcache_linesize), tmp1 ;\
59 ld [tmp1 + %lo(dcache_linesize)], tmp1 ;\
73 * tmp1 = cache line size \
75 sub tmp3, tmp1, tmp2 ;\
81 sub tmp2, tmp1, tmp2 ;\
88 * tmp1 = cache line size \
95 sub tmp3, tmp1, tmp3 ;\
109 sub tmp3, tmp1, tmp3 ;\
115 * tmp1 = cache line size \
121 sub tmp3, tmp1, arg2 ;\
135 sub arg2, tmp1, arg2 ;\
141 #define DCACHE_FLUSHCOLOR(arg, tmp1, tmp2) \
142 ldxa [%g0]ASI_LSU, tmp1; \
143 btst LSU_DC, tmp1; /* is dcache enabled? */ \
145 sethi %hi(dcache_linesize), tmp1; \
146 ld [tmp1 + %lo(dcache_linesize)], tmp1; \
151 * tmp1 = cache line size \
154 sub tmp2, tmp1, tmp2; \
160 sub tmp2, tmp1, tmp2; \
198 #define SF_WORKAROUND(tmp1, tmp2) \
200 set MMU_PCONTEXT, tmp1 ;\
201 stxa %g0, [tmp1]ASI_DMMU ;\
204 #define SF_WORKAROUND(tmp1, tmp2)
215 #define VTAG_FLUSHUPAGE(lbl, arg1, arg2, tmp1, tmp2, tmp3, tmp4) \
216 rdpr %pstate, tmp1 ;\
217 andn tmp1, PSTATE_IE, tmp2 ;\
236 wrpr %g0, tmp1, %pstate
247 #define DTLB_FLUSH_UNLOCKED_UCTXS(lbl, arg1, tmp1, tmp2, tmp3, \
251 SF_WORKAROUND(tmp1, tmp2) ;\
260 set TAGREAD_CTX_MASK, tmp1 ;\
262 and tmp2, tmp1, tmp6 ;\
263 andn tmp2, tmp1, tmp5 ;\
268 VTAG_FLUSHUPAGE(VD/**/lbl, tmp5, tmp6, tmp1, tmp2, tmp3, tmp4) ;\
282 #define ITLB_FLUSH_UNLOCKED_UCTXS(lbl, arg1, tmp1, tmp2, tmp3, \
286 SF_WORKAROUND(tmp1, tmp2) ;\
295 set TAGREAD_CTX_MASK, tmp1 ;\
297 and tmp2, tmp1, tmp6 ;\
298 andn tmp2, tmp1, tmp5 ;\
303 VTAG_FLUSHUPAGE(VI/**/lbl, tmp5, tmp6, tmp1, tmp2, tmp3, tmp4) ;\