Lines Matching refs:g5
565 ldxa [%g4]ASI_DMMU, %g5 /* rd old ctxnum */
570 stxa %g5, [%g4]ASI_DMMU /* restore old ctxnum */
600 SFMMU_CPU_CNUM(%g2, %g5, %g6) ! %g5 = sfmmu cnum on this CPU
605 stxa %g5, [%g4]ASI_DMMU /* write new ctxum */
608 sethi %hi(FLUSH_ADDR), %g5
612 flush %g5
662 DCACHE_FLUSHPAGE(%g1, %g2, %g3, %g4, %g5)
821 andn %g4, PSTATE_IE, %g5
822 wrpr %g0, %g5, %pstate ! disable interrupts
825 or %g0, 1, %g5
826 sllx %g5, HB_UPA_DMAP_DATA_BIT, %g5
828 or %g1, %g5, %g5
830 stxa %g5, [%g0]ASI_UPA_CONFIG ! enable direct map for data access
834 mov HB_ECACHE_FLUSH_CNT-1, %g5
842 brgz,a,pt %g5, 2b
843 dec %g5
982 * %g5 will have the trap type (with 0x200 set if we're at TL > 0).
1032 or %g0, 0x63, %g5 ! pass along the CE ttype
1046 ldxa [%g4]ASI_SDB_INTR_R, %g5 ! read sdb upper half into g5
1049 andcc %g5, %g6, %g1 ! check for CE in upper half
1050 sllx %g5, 33, %g5 ! shift upper bits to <42:33>
1051 or %g3, %g5, %g3 ! or with afsr bits
1058 ldxa [%g4]ASI_SDB_INTR_R, %g5 ! read sdb lower half into g6
1059 andcc %g5, %g6, %g1 ! check for CE in lower half
1060 sllx %g5, 43, %g5 ! shift upper bits to <52:43>
1061 or %g3, %g5, %g3 ! or with afsr bits
1076 sethi %hi(sys_trap), %g5
1077 jmp %g5 + %lo(sys_trap) ! goto sys_trap
1123 sllx %g5, 53, %g5 ! move ttype to <63:53>
1124 or %g3, %g5, %g3 ! or to afsr in g3
1133 ldxa [%g4]ASI_SDB_INTR_R, %g5 ! read sdb upper half into 56
1136 andcc %g5, %g6, %g1 ! check for UE in upper half
1137 sllx %g5, 33, %g5 ! shift upper bits to <42:33>
1138 or %g3, %g5, %g3 ! or with afsr bits
1145 ldxa [%g4]ASI_SDB_INTR_R, %g5 ! read sdb lower half into g5
1146 andcc %g5, %g6, %g1 ! check for UE in lower half
1147 sllx %g5, 43, %g5 ! shift upper bits to <52:43>
1148 or %g3, %g5, %g3 ! or with afsr bits
1157 RESET_USER_RTT_REGS(%g4, %g5, async_err_resetskip)
1161 sethi %hi(sys_trap), %g5
1162 jmp %g5 + %lo(sys_trap) ! goto sys_trap
1173 ldxa [%g4]ASI_SDB_INTR_R, %g5 ! read sdb upper half into g5
1174 sllx %g5, 33, %g5 ! shift upper bits to <42:33>
1175 or %g3, %g5, %g3 ! or with afsr bits
1177 ldxa [%g4]ASI_SDB_INTR_R, %g5 ! read sdb lower half into g5
1178 sllx %g5, 43, %g5 ! shift upper bits to <52:43>
1179 or %g3, %g5, %g3 ! or with afsr bits
1181 RESET_USER_RTT_REGS(%g4, %g5, dis_err_panic1_resetskip)
1184 sethi %hi(sys_trap), %g5
1185 jmp %g5 + %lo(sys_trap) ! goto sys_trap
1550 * %g5 temp
1553 sethi %hi(ecache_associativity), %g5
1554 ld [%g5 + %lo(ecache_associativity)], %g5
1555 udivx %o2, %g5, %g2 ! set size (i.e. ecache_size/#sets)
1569 or %g0, 1, %g5
1570 sllx %g5, HB_UPA_DMAP_DATA_BIT, %g5
1572 or %g1, %g5, %g5
1574 stxa %g5, [%g0]ASI_UPA_CONFIG ! enable direct map for data access
1583 or %o1, %g0, %g5 ! starting aliased offset
1585 ldxa [%g5 + %o3]ASI_MEM, %g0 ! load ecache_flushaddr + alias
1587 add %g5, %g2, %g5 ! calculate offset in next set
1588 and %g5, %g3, %g5 ! force offset within aliased range
1589 cmp %g5, %o5 ! skip loads from physaddr
1690 * %g5 temp
1694 sethi %hi(ecache_associativity), %g5
1695 ld [%g5 + %lo(ecache_associativity)], %g5
1696 udivx %o2, %g5, %g2 ! set size (i.e. ecache_size/#sets)
1711 or %g0, 1, %g5
1712 sllx %g5, HB_UPA_DMAP_DATA_BIT, %g5
1714 or %g1, %g5, %g5
1716 stxa %g5, [%g0]ASI_UPA_CONFIG ! enable direct map for data access
1734 or %o1, %g0, %g5 ! starting offset
1736 ldxa [%g5 + %o3]ASI_MEM, %g0 ! load ecache_flushaddr + alias
1738 add %g5, %g2, %g5 ! calculate offset in next set
1739 and %g5, %g3, %g5 ! force offset within aliased range
1740 cmp %g5, %o5 ! skip loads from physaddr
1826 * %g5 temp
1829 sethi %hi(ecache_associativity), %g5
1830 ld [%g5 + %lo(ecache_associativity)], %g5
1831 udivx %o2, %g5, %g2 ! set size (i.e. ecache_size/#sets)
1845 or %g0, 1, %g5
1846 sllx %g5, HB_UPA_DMAP_DATA_BIT, %g5
1848 or %g4, %g5, %g5
1850 stxa %g5, [%g0]ASI_UPA_CONFIG ! enable direct map for data access
1861 mov HB_PHYS_FLUSH_CNT-1, %g5 ! #loads to flush physaddr
1871 brgz,pt %g5, 2b
1872 dec %g5
1908 ! %g2, %g3, %g5 - scratch
1914 GET_CPU_PRIVATE_PTR(%g2, %g4, %g5, 1f);