Lines Matching refs:g1
455 PANIC_IF_INTR_DISABLED_PSTR(%o5, sfdi_label1, %g1)
488 SFMMU_CPU_CNUM(%o1, %g1, %g2) /* %g1 = sfmmu cnum on this CPU */
493 cmp %o2, %g1
496 stxa %g1, [%o4]ASI_DMMU /* wr new ctxum */
524 CPU_INDEX(%g1, %g2)
525 mulx %g1, CPU_NODE_SIZE, %g1
527 add %g1, %g2, %g1
528 lduh [%g1 + ITLB_SIZE], %g2 ! %g2 = # entries in ITLB
529 lduh [%g1 + DTLB_SIZE], %g1 ! %g1 = # entries in DTLB
531 sub %g1, 1, %g1 ! %g1 = # entries in DTLB - 1
541 DTLB_FLUSH_UNLOCKED_UCTXS(D, %g1, %g3, %g4, %o2, %o3, %o4, %o5)
553 * %g1 = vaddr, zero-extended on 32-bit kernel
558 srln %g1, MMU_PAGESHIFT, %g1
559 slln %g1, MMU_PAGESHIFT, %g1 /* g1 = vaddr */
566 or DEMAP_SECOND | DEMAP_PAGE_TYPE, %g1, %g1
568 stxa %g0, [%g1]ASI_DTLB_DEMAP
569 stxa %g0, [%g1]ASI_ITLB_DEMAP
579 * %g1 = vaddr, zero-extended on 32-bit kernel
590 srln %g1, MMU_PAGESHIFT, %g1
591 slln %g1, MMU_PAGESHIFT, %g1 /* g1 = vaddr */
592 or DEMAP_SECOND | DEMAP_PAGE_TYPE, %g1, %g1
610 stxa %g0, [%g1]ASI_DTLB_DEMAP
611 stxa %g0, [%g1]ASI_ITLB_DEMAP
615 add %g1, %g2, %g1 /* go to nextpage */
660 * %g1 = pfnum, %g2 = color
662 DCACHE_FLUSHPAGE(%g1, %g2, %g3, %g4, %g5)
677 * %g1 = vcolor
679 DCACHE_FLUSHCOLOR(%g1, %g2, %g3)
695 ldxa [%g0]ASI_INTR_DISPATCH_STATUS, %g1
697 btst IDSR_BUSY, %g1
718 ldxa [%g0]ASI_INTR_DISPATCH_STATUS, %g1
719 btst IDSR_BUSY, %g1
733 mov IDDR_0, %g1
736 stxa %o0, [%g1]ASI_INTR_DISPATCH
756 sll %o0, IDCR_PID_SHIFT, %g1 ! IDCR<18:14> = upa id
757 or %g1, IDCR_OFFSET, %g1 ! IDCR<13:0> = 0x70
758 stxa %g0, [%g1]ASI_INTR_DISPATCH ! interrupt vector dispatch
827 ldxa [%g0]ASI_UPA_CONFIG, %g1 ! current UPA config (restored later)
828 or %g1, %g5, %g5
846 stxa %g1, [%g0]ASI_UPA_CONFIG ! restore UPA config reg
860 DCACHE_FLUSHALL(%o0, %o1, %g1)
861 ICACHE_FLUSHALL(%o2, %o3, %g1)
906 ldxa [%g0]ASI_ESTATE_ERR, %g1
953 stxa %g1, [%g0]ASI_ESTATE_ERR ! restore error enable
1028 or %g0, 1, %g1 ! put 1 in g1
1029 sllx %g1, 21, %g1 ! shift left to <21> afsr UE
1030 andcc %g1, %g3, %g0 ! check for UE in afsr
1049 andcc %g5, %g6, %g1 ! check for CE in upper half
1054 stxa %g1, [%g4]ASI_SDB_INTR_W ! clear sdb reg error bit
1059 andcc %g5, %g6, %g1 ! check for CE in lower half
1064 stxa %g1, [%g4]ASI_SDB_INTR_W ! clear sdb reg error bit
1072 set cpu_ce_error, %g1 ! put *cpu_ce_error() in g1
1088 set ce_trap_tl1, %g1
1126 or %g0, 1, %g1 ! put 1 in g1
1127 sllx %g1, 21, %g1 ! shift left to <21> afsr UE
1128 andcc %g1, %g3, %g0 ! check for UE in afsr
1136 andcc %g5, %g6, %g1 ! check for UE in upper half
1141 stxa %g1, [%g4]ASI_SDB_INTR_W ! clear sdb reg UE error bit
1146 andcc %g5, %g6, %g1 ! check for UE in lower half
1151 stxa %g1, [%g4]ASI_SDB_INTR_W ! clear sdb reg UE error bit
1160 set cpu_async_error, %g1 ! put cpu_async_error in g1
1169 ! save destination routine is in g1
1254 set MMU_PCONTEXT, %g1
1255 stxa %g0, [%g1]ASI_DMMU ! KCONTEXT
1258 ldxa [%o0]ASI_ITLB_ACCESS, %g1
1261 andn %g1, %g2, %g1 ! for details
1262 stx %g1, [%o1]
1274 set MMU_PCONTEXT, %g1
1275 stxa %g0, [%g1]ASI_DMMU ! KCONTEXT
1278 ldxa [%o0]ASI_DTLB_ACCESS, %g1
1281 andn %g1, %g2, %g1 ! itlb_rd_entry
1282 stx %g1, [%o1]
1332 rdpr %pstate, %g1 /* save processor state */
1333 andn %g1, PSTATE_IE, %g3 /* turn off */
1350 wrpr %g0, %g1, %pstate /* restore processor state */
1369 ldxa [%g0]ASI_ESTATE_ERR, %g1
1399 stxa %g1, [%g0]ASI_ESTATE_ERR ! Turn error enable back on
1421 ldxa [%g0]ASI_ESTATE_ERR, %g1
1456 stxa %g1, [%g0]ASI_ESTATE_ERR ! Turn error enable back on
1546 * %g1 UPA config (restored later)
1571 ldxa [%g0]ASI_UPA_CONFIG, %g1 ! current UPA config (restored later)
1572 or %g1, %g5, %g5
1603 stxa %g1, [%g0]ASI_UPA_CONFIG ! restore UPA config (DM bits)
1649 ldxa [%g0]ASI_ESTATE_ERR, %g1
1665 stxa %g1, [%g0]ASI_ESTATE_ERR ! restore error enable
1686 * %g1 UPA config (restored later)
1713 ldxa [%g0]ASI_UPA_CONFIG, %g1 ! current UPA config (restored later)
1714 or %g1, %g5, %g5
1754 stxa %g1, [%g0]ASI_UPA_CONFIG ! restore UPA config (DM bits)
1796 ldxa [%g0]ASI_ESTATE_ERR, %g1
1802 stxa %g1, [%g0]ASI_ESTATE_ERR ! restore error enable
1822 * %g1 error enable register
1853 ldxa [%g0]ASI_ESTATE_ERR, %g1
1875 stxa %g1, [%g0]ASI_ESTATE_ERR ! restore error enable
1905 ! %g1 - inum
1924 jmp %g6 ! setsoftint_tl1(%g1) - queue intr_vec
1954 ldxa [%g0]ASI_ESTATE_ERR, %g1
1973 stxa %g1, [%g0]ASI_ESTATE_ERR ! Turn error enable back on
2002 ldxa [%g0]ASI_ESTATE_ERR, %g1
2026 stxa %g1, [%g0]ASI_ESTATE_ERR ! Turn error enable back on