Lines Matching refs:REALSRC
1263 #define REALSRC %i0
1281 ldub [REALSRC], SRC ! move 4 bytes per loop iteration
1284 ldub [REALSRC + 1], SRC
1285 add REALSRC, 4, REALSRC
1287 ldub [REALSRC - 2], SRC
1290 ldub [REALSRC - 1], SRC
1297 1: ldub [REALSRC], SRC
1298 inc REALSRC
1306 andn REALSRC, 0x7, SRC
1312 alignaddr REALSRC, %g0, %g0
1336 add REALSRC, VIS_BLOCKSIZE, REALSRC
1360 add REALSRC, VIS_BLOCKSIZE, REALSRC
1368 ! only if REALSRC & 0x7 is 0
1371 andcc REALSRC, 0x7, %g0
1400 add REALSRC, VIS_BLOCKSIZE, REALSRC
1413 5: ldub [REALSRC], TMP
1414 inc REALSRC
1540 mov REALSRC, SRC
2206 ldub [REALSRC], SRC ! move 4 bytes per loop iteration
2209 ldub [REALSRC + 1], SRC
2210 add REALSRC, 4, REALSRC
2212 ldub [REALSRC - 2], SRC
2215 ldub [REALSRC - 1], SRC
2222 1: ldub [REALSRC], SRC
2223 inc REALSRC
2231 andn REALSRC, 0x7, SRC
2237 alignaddr REALSRC, %g0, %g0
2261 add REALSRC, VIS_BLOCKSIZE, REALSRC
2285 add REALSRC, VIS_BLOCKSIZE, REALSRC
2293 ! only if REALSRC & 0x7 is 0
2296 andcc REALSRC, 0x7, %g0
2325 add REALSRC, VIS_BLOCKSIZE, REALSRC
2338 5: ldub [REALSRC], TMP
2339 inc REALSRC
2985 lduba [REALSRC]%asi, SRC ! move 4 bytes per loop iteration
2988 lduba [REALSRC + 1]%asi, SRC
2989 add REALSRC, 4, REALSRC
2991 lduba [REALSRC - 2]%asi, SRC
2994 lduba [REALSRC - 1]%asi, SRC
3001 1: lduba [REALSRC]%asi, SRC
3002 inc REALSRC
3010 andn REALSRC, 0x7, SRC
3016 alignaddr REALSRC, %g0, %g0
3040 add REALSRC, VIS_BLOCKSIZE, REALSRC
3064 add REALSRC, VIS_BLOCKSIZE, REALSRC
3072 ! only if REALSRC & 0x7 is 0
3075 andcc REALSRC, 0x7, %g0
3104 add REALSRC, VIS_BLOCKSIZE, REALSRC
3117 5: lduba [REALSRC]ASI_USER, TMP
3118 inc REALSRC