Lines Matching refs:g3
195 sethi %hi(ksfmmup), %g3
196 ldx [%g3 + %lo(ksfmmup)], %g3
197 cmp %g3, %g2
210 SFMMU_CPU_CNUM(%g2, %g6, %g3) ! %g6 = sfmmu cnum on this CPU
256 and %g4, %g2, %g3 /* g3 = pgcnt - 1 */
257 add %g3, 1, %g3 /* g3 = pgcnt */
277 deccc %g3 /* decr pgcnt */
286 * g3 = pgcnt
310 deccc %g3 /* decr pgcnt */
490 mov IDDR_2, %g3
501 stxa %o2, [%g3]ASI_INTR_DISPATCH
884 mov %g0, %g3 ;\
1157 rdpr %tt, %g3
1179 rdpr %tt, %g3
1204 rdpr %tt, %g3
1236 * 1. Save globals %g1, %g2 & %g3 onto the scratchpad regs.
1267 * %g1, %g2 & %g3 whenever we enter this trap handler.
1287 OPL_TRAPTRACE(%g1, %g2, %g3, opl_sync_trap_lb)
1292 mov MMU_SFSR, %g3
1293 ldxa [%g3]ASI_IMMU, %g1 ! IAE trap case tt = 0xa
1298 sethi %hi(SFSR_UE|SFSR_BERR|SFSR_TO), %g3
1299 andcc %g1, %g3, %g0 ! Check for UE/BERR/TO errors
1302 set OPL_MMU_SFPAR, %g3 ! In the UE/BERR/TO cases, use
1304 ldxa [%g3]ASI_IMMU, %g2
1306 ldxa [%g3]ASI_DMMU, %g1 ! DAE trap case tt = 0x32
1313 sethi %hi(SFSR_UE|SFSR_BERR|SFSR_TO), %g3
1314 andcc %g1, %g3, %g0 ! Check UE/BERR/TO for valid SFPAR
1318 sethi %hi(SFSR_TLB_PRT), %g3
1319 andcc %g1, %g3, %g0
1325 * Only %g1, %g2 and %g3 are allowed
1327 FLUSH_ALL_TLB(%g3)
1328 set OPL_SCRATCHPAD_ERRLOG, %g3
1329 ldxa [%g3]ASI_SCRATCHPAD, %g3 ! Read errlog scratchreg
1330 and %g3, ERRLOG_REG_NUMERR_MASK, %g3! Extract the error count
1331 subcc %g3, 1, %g0 ! Subtract one from the count
1334 LOG_SYNC_REG(%g1, %g2, %g3) ! Record into the error log
1335 set OPL_SCRATCHPAD_ERRLOG, %g3
1336 ldxa [%g3]ASI_SCRATCHPAD, %g2
1338 stxa %g2, [%g3]ASI_SCRATCHPAD ! update the errlog scratchreg
1339 OPL_RESTORE_GLOBAL(%g1, %g2, %g3)
1342 sethi %hi(SFSR_TLB_MUL), %g3
1343 andcc %g1, %g3, %g0
1346 FLUSH_ALL_TLB(%g3)
1355 LOG_SYNC_REG(%g1, %g2, %g3) ! Record into the error log
1382 RESET_USER_RTT_REGS(%g2, %g3, opl_sync_trap_resetskip)
1384 mov %g5, %g3 ! pass SFSR to the 3rd arg
1393 mov %g5, %g3 ! pass SFSR to the 3rd arg
1461 ldxa [%g2]ASI_AFSR, %g3 ! Enable Weak error
1462 or %g3, ASI_ECR_WEAK_ED, %g3 ! detect mode to prevent
1463 stxa %g3, [%g2]ASI_AFSR ! potential error storms
1482 FLUSH_ALL_TLB(%g3)
1483 rdpr %tl, %g3 ! Read TL
1484 cmp %g3, 1 ! Check if we came from TL=0
1492 set OPL_SCRATCHPAD_ERRLOG, %g3
1493 ldxa [%g3]ASI_SCRATCHPAD, %g2 ! Read errlog scratch reg
1494 and %g2, ERRLOG_REG_NUMERR_MASK, %g3! Extract error count and
1495 subcc %g3, 1, %g3 ! subtract one from it
1499 set OPL_SCRATCHPAD_ERRLOG, %g3 ! and write back the updated
1500 stxa %g2, [%g3]ASI_SCRATCHPAD ! count into the errlog reg
1501 LOG_UGER_REG(%g1, %g2, %g3) ! Log the error info
1503 OPL_TRAPTRACE(%g1, %g2, %g3, opl_uger_trap_lb)
1521 IAG_CRE(%g2, %g3)
1523 ldxa [%g2]ASI_AFSR, %g3
1524 or %g3, ASI_ECR_WEAK_ED, %g3
1525 stxa %g3, [%g2]ASI_AFSR
1540 RESET_MMU_REGS(%g2, %g3, %g4)
1561 RESET_MMU_REGS(%g2, %g3, %g4)
1579 RESET_PREV_TSTATE(%g2, %g3, opl_uger_tstate_1)
1603 LOG_UGER_REG(%g1, %g3, %g4)
1609 LOG_UGER_REG(%g1, %g3, %g4)
1610 RESET_TO_PRIV(%g1, %g3, %g4, %l0)
1619 rdpr %tl, %g3 ! arg #2
1697 mov T_FLUSHW, %g3
1715 mov T_FLUSHW, %g3
1743 OPL_SAVE_GLOBAL(%g1,%g2,%g3)
1744 sethi %hi(opl_sync_trap), %g3
1745 jmp %g3 + %lo(opl_sync_trap)
1763 sethi %hi(opl_uger_trap), %g3
1764 jmp %g3 + %lo(opl_uger_trap)
1782 sethi %hi(opl_ta3_trap), %g3
1783 jmp %g3 + %lo(opl_ta3_trap)
1801 sethi %hi(opl_cleanw_subr), %g3
1802 add %g3, %lo(opl_cleanw_subr), %g3
1803 jmpl %g3, %g7
1850 andn %g1, PSTATE_IE, %g3
1852 wrpr %g0, %g3, %pstate ! turn off interrupts
2086 andn %g1, PSTATE_IE, %g3 /* turn off */
2087 wrpr %g0, %g3, %pstate /* interrupts */
2090 mov 1, %g3 /* create mask */
2091 sllx %g3, 63, %g3 /* for NPT bit */
2096 wrpr %g3, %g2, %tick /* write tick register, */
2101 mov 1, %g3 /* create mask */
2102 sllx %g3, 63, %g3 /* for NPT bit */
2107 wr %g3, %g2, STICK /* write stick register, */