Lines Matching defs:inst
91 vis_inst_type inst;
100 if ((f.inst.opf & 1) == 0) { /* double precision */
109 switch (f.inst.opf) {
123 ftt = vis_edge(pfpsd, f.inst, pregs, prw);
128 ftt = vis_array(pfpsd, f.inst, pregs, prw);
132 ftt = vis_alignaddr(pfpsd, f.inst, pregs, prw, fp);
135 ftt = vis_bmask(pfpsd, f.inst, pregs, prw, fp);
145 ftt = vis_fcmp(pfpsd, f.inst, pregs, prw);
154 ftt = vis_fmul(pfpsd, f.inst);
161 ftt = vis_fpixel(pfpsd, f.inst, fp);
165 ftt = vis_pdist(pfpsd, pinst, pregs, prw, f.inst.opf);
181 ftt = vis_fpaddsub(pfpsd, f.inst);
356 ftt = vis_siam(pfpsd, f.inst, fp);
373 vis_inst_type inst, /* FPU instruction to simulate. */
385 nrs1 = inst.rs1;
386 nrs2 = inst.rs2;
387 nrd = inst.rd;
406 switch (inst.opf) {
412 switch (inst.opf) {
415 if (inst.opf == edge8) {
428 if (inst.opf == edge8l) {
447 switch (inst.opf) {
450 if (inst.opf == edge16) {
465 if (inst.opf == edge16l) {
488 switch (inst.opf) {
491 if (inst.opf == edge32) {
506 if (inst.opf == edge32l) {
525 switch (inst.opf) {
550 vis_inst_type inst, /* FPU instruction to simulate. */
561 nrs1 = inst.rs1;
562 nrs2 = inst.rs2;
563 nrd = inst.rd;
590 switch (inst.opf) {
615 vis_inst_type inst, /* FPU instruction to simulate. */
625 nrs1 = inst.rs1;
626 nrs2 = inst.rs2;
627 nrd = inst.rd;
643 if (inst.opf == alignaddrl) {
662 vis_inst_type inst, /* FPU instruction to simulate. */
672 nrs1 = inst.rs1;
673 nrs2 = inst.rs2;
674 nrd = inst.rd;
700 vis_inst_type inst) /* FPU instruction to simulate. */
714 nrs1 = inst.rs1;
715 nrs2 = inst.rs2;
716 nrd = inst.rd;
717 if ((inst.opf & 1) == 0) { /* double precision */
725 switch (inst.opf) {
796 vis_inst_type inst, /* FPU instruction to simulate. */
810 nrs1 = inst.rs1;
811 nrs2 = inst.rs2;
812 nrd = inst.rd;
821 switch (inst.opf) {
905 vis_inst_type inst) /* FPU instruction to simulate. */
924 nrs1 = inst.rs1;
925 nrs2 = inst.rs2;
926 nrd = inst.rd;
927 if ((inst.opf & 1) == 0) { /* double precision */
932 switch (inst.opf) {
1056 vis_inst_type inst, /* FPU instruction to simulate. */
1077 nrs1 = inst.rs1;
1078 nrs2 = inst.rs2;
1079 nrd = inst.rd;
1080 if ((inst.opf != fpack16) && (inst.opf != fpackfix)) {
1085 switch (inst.opf) {
1351 vis_inst_type inst, /* FPU instruction to simulate. */
1356 nrs2 = inst.rs2;
1378 vis_inst_type inst;
1397 return (vis_prtl_fst(pfpsd, i.inst, pregs,
1407 return (vis_short_fls(pfpsd, i.inst, pregs,
1419 return (vis_blk_fldst(pfpsd, i.inst, pregs,
1432 vis_inst_type inst, /* ISE instruction to simulate. */
1450 nrs1 = inst.rs1;
1451 nrs2 = inst.rs2;
1452 nrd = inst.rd;
1455 opf = inst.opf;
1594 vis_inst_type inst, /* ISE instruction to simulate. */
1610 vis_inst_type inst;
1617 nrs1 = inst.rs1;
1618 nrs2 = inst.rs2;
1619 nrd = inst.rd;
1622 opf = inst.opf;
1623 fp.inst = inst;
1633 fp.inst = inst;
1649 if ((inst.op3 & 7) == 3) { /* load byte */
1666 if ((inst.op3 & 7) == 3) { /* load short */
1683 if ((inst.op3 & 7) == 3) { /* load short */
1713 vis_inst_type inst, /* ISE instruction to simulate. */
1727 vis_inst_type inst;
1733 nrs1 = inst.rs1;
1734 nrs2 = inst.rs2;
1735 nrd = inst.rd;
1743 opf = inst.opf;
1753 fp.inst = inst;
1777 if ((inst.op3 & 7) == 3) { /* lddf */
1812 /* addr of unimp inst */
1874 fp_inst_type inst;
1878 fp.inst = pinst; /* Extract simm13 field */