Lines Matching refs:os1
178 * os1, os2, os3: scratch registers, may be out
181 #define SERVE_INTR_PRE(iv_p, cpu, ls1, ls2, os1, os2, os3, regs) \
184 SERVE_INTR_TRACE(iv_p, os1, os2, os3, regs);
208 #define SERVE_INTR(os5, cpu, ls1, ls2, os1, os2, os3, os4) \
221 sll ls1, 3, os1; \
222 add os1, CPU_STATS_SYS_INTR - 8, os2; \
227 add cpu, INTR_HEAD, os1; \
228 add os1, os2, os1; \
229 ldn [os1], os3;
237 * os1, os2, os4, os5 - scratch reg, can be out (not preserved)
239 #define SERVE_INTR_NEXT(os5, cpu, ls1, ls2, os1, os2, os3, os4) \
241 add cpu, INTR_HEAD, os1; \
253 stn os5, [os1 + os4]; \
254 add cpu, INTR_TAIL, os1; \
255 stn %g0, [os1 + os4]; \
256 mov 1, os1; \
257 sll os1, ls1, os1; \
258 wr os1, CLEAR_SOFTINT; \
266 SERVE_INTR_TRACE2(os5, os1, os2, os3, os4);
272 #define SERVE_INTR_TRACE(inum, os1, os2, os3, os4) \
276 TRACE_PTR(os1, os2); \
278 stna os2, [os1 + TRAP_ENT_TPC]%asi; \
280 stxa os2, [os1 + TRAP_ENT_TSTATE]%asi; \
283 stxa os2, [os1 + TRAP_ENT_TICK]%asi; \
284 TRACE_SAVE_TL_GL_REGS(os1, os2); \
288 stha os2, [os1 + TRAP_ENT_TT]%asi; \
289 stna %sp, [os1 + TRAP_ENT_SP]%asi; \
290 stna inum, [os1 + TRAP_ENT_TR]%asi; \
291 stna %g0, [os1 + TRAP_ENT_F1]%asi; \
292 stna %g0, [os1 + TRAP_ENT_F2]%asi; \
293 stna %g0, [os1 + TRAP_ENT_F3]%asi; \
294 stna %g0, [os1 + TRAP_ENT_F4]%asi; \
295 TRACE_NEXT(os1, os2, os3); \
298 #define SERVE_INTR_TRACE(inum, os1, os2, os3, os4)
305 #define SERVE_INTR_TRACE2(inum, os1, os2, os3, os4) \
309 TRACE_PTR(os1, os2); \
310 stna %g0, [os1 + TRAP_ENT_TPC]%asi; \
311 stxa %g0, [os1 + TRAP_ENT_TSTATE]%asi; \
314 stxa os2, [os1 + TRAP_ENT_TICK]%asi; \
315 TRACE_SAVE_TL_GL_REGS(os1, os2); \
319 stha os2, [os1 + TRAP_ENT_TT]%asi; \
320 stna %sp, [os1 + TRAP_ENT_SP]%asi; \
321 stna inum, [os1 + TRAP_ENT_TR]%asi; \
322 stna %g0, [os1 + TRAP_ENT_F1]%asi; \
323 stna %g0, [os1 + TRAP_ENT_F2]%asi; \
324 stna %g0, [os1 + TRAP_ENT_F3]%asi; \
325 stna %g0, [os1 + TRAP_ENT_F4]%asi; \
326 TRACE_NEXT(os1, os2, os3); \
329 #define SERVE_INTR_TRACE2(inum, os1, os2, os3, os4)