Lines Matching refs:g6
65 ! %g3, %g5, %g6, %g7 - temps
76 add %g1, INTR_HEAD, %g6 ! %g6 = &cpu->m_cpu.intr_head
77 add %g6, %g5, %g6 ! %g6 = &cpu->m_cpu.intr_head[pil]
78 ldn [%g6], %g2 ! %g2 = cpu->m_cpu.intr_head[pil]
94 stn %g3, [%g6] ! update cpu->m_cpu.intr_head[pil]
95 add %g1, INTR_TAIL, %g6 ! %g6 = &cpu->m_cpu.intr_tail
96 stn %g0, [%g5 + %g6] ! clear cpu->m_cpu.intr_tail[pil]
102 TRACE_PTR(%g5, %g6)
103 TRACE_SAVE_TL_GL_REGS(%g5, %g6)
104 rdpr %tt, %g6
105 stha %g6, [%g5 + TRAP_ENT_TT]%asi ! trap_type = %tt
106 rdpr %tpc, %g6
107 stna %g6, [%g5 + TRAP_ENT_TPC]%asi ! trap_pc = %tpc
108 rdpr %tstate, %g6
109 stxa %g6, [%g5 + TRAP_ENT_TSTATE]%asi ! trap_tstate = %tstate
113 GET_TRACE_TICK(%g6, %g3)
114 stxa %g6, [%g5 + TRAP_ENT_TICK]%asi ! trap_tick = %tick
116 add %g1, INTR_HEAD, %g6
117 ldn [%g6 + %g3], %g6 ! %g6=cpu->m_cpu.intr_head[pil]
118 stna %g6, [%g5 + TRAP_ENT_F2]%asi ! trap_f2 = intr_head[pil]
119 add %g1, INTR_TAIL, %g6
120 ldn [%g6 + %g3], %g6 ! %g6=cpu->m_cpu.intr_tail[pil]
121 stna %g6, [%g5 + TRAP_ENT_F3]%asi ! trap_f3 = intr_tail[pil]
123 TRACE_NEXT(%g5, %g6, %g3)
1644 add %g4, INTR_TAIL, %g6 ! %g6 = &cpu->m_cpu.intr_tail
1645 ldn [%g6 + %g7], %g5 ! %g5 = cpu->m_cpu.intr_tail[pil]
1648 stn %g1, [%g6 + %g7] ! make intr_rec_t (iv) as new tail
1652 lduh [%g5 + IV_FLAGS], %g6 ! %g6 = ct->iv_flags
1653 and %g6, IV_SOFTINT_MT, %g6 ! %g6 = ct->iv_flags & IV_SOFTINT_MT
1654 brz,pt %g6, 0f ! check for Multi target softint flag
1656 ld [%g4 + CPU_ID], %g6 ! for multi target softint, use cpuid
1657 sll %g6, CPTRSHIFT, %g6 ! calculate offset address from cpuid
1658 add %g3, %g6, %g3 ! %g3 = &ct->iv_xpil_next[cpuid]
1669 add %g4, INTR_HEAD, %g6 ! %g6 = &cpu->m_cpu.intr_head[pil]
1670 stn %g1, [%g6 + %g7] ! cpu->m_cpu.intr_head[pil] = iv
1673 TRACE_PTR(%g5, %g6)
1674 GET_TRACE_TICK(%g6, %g3)
1675 stxa %g6, [%g5 + TRAP_ENT_TICK]%asi ! trap_tick = %tick
1676 TRACE_SAVE_TL_GL_REGS(%g5, %g6)
1677 rdpr %tt, %g6
1678 stha %g6, [%g5 + TRAP_ENT_TT]%asi ! trap_type = %tt
1679 rdpr %tpc, %g6
1680 stna %g6, [%g5 + TRAP_ENT_TPC]%asi ! trap_pc = %tpc
1681 rdpr %tstate, %g6
1682 stxa %g6, [%g5 + TRAP_ENT_TSTATE]%asi ! trap_tstate = %tstate
1685 ldn [%g1 + IV_PIL_NEXT], %g6 !
1686 stna %g6, [%g5 + TRAP_ENT_F1]%asi ! trap_f1 = iv->iv_pil_next
1687 add %g4, INTR_HEAD, %g6
1688 ldn [%g6 + %g7], %g6 ! %g6=cpu->m_cpu.intr_head[pil]
1689 stna %g6, [%g5 + TRAP_ENT_F2]%asi ! trap_f2 = intr_head[pil]
1690 add %g4, INTR_TAIL, %g6
1691 ldn [%g6 + %g7], %g6 ! %g6=cpu->m_cpu.intr_tail[pil]
1692 stna %g6, [%g5 + TRAP_ENT_F3]%asi ! trap_f3 = intr_tail[pil]
1694 TRACE_NEXT(%g5, %g6, %g3)
1726 ! %g5, %g6,%g7 - temps
1745 sll %g1, CPTRSHIFT, %g6 ! %g6 = offset to inum entry in table
1746 add %g5, %g6, %g5 ! %g5 = &intr_vec_table[inum]
1778 add %g4, INTR_TAIL, %g6 ! %g6 = &cpu->m_cpu.intr_tail
1779 ldn [%g6 + %g7], %g5 ! %g5 = cpu->m_cpu.intr_tail[pil]
1782 stn %g3, [%g6 + %g7] ! make intr_vec_t (iv) as new tail
1787 lduh [%g5 + IV_FLAGS], %g6 ! %g6 = ct->iv_flags
1788 and %g6, IV_SOFTINT_MT, %g6 ! %g6 = ct->iv_flags & IV_SOFTINT_MT
1789 brz,pt %g6, 1f ! check for Multi target softint flag
1791 ld [%g4 + CPU_ID], %g6 ! for multi target softint, use cpuid
1792 sll %g6, CPTRSHIFT, %g6 ! calculate offset address from cpuid
1793 add %g5, %g6, %g5 ! %g5 = &ct->iv_xpil_next[cpuid]
1804 add %g4, INTR_HEAD, %g6 ! %g6 = &cpu->m_cpu.intr_head[pil]
1805 stn %g3, [%g6 + %g7] ! cpu->m_cpu.intr_head[pil] = iv
1808 TRACE_PTR(%g5, %g6)
1809 TRACE_SAVE_TL_GL_REGS(%g5, %g6)
1810 rdpr %tt, %g6
1811 stha %g6, [%g5 + TRAP_ENT_TT]%asi ! trap_type = %tt`
1812 rdpr %tpc, %g6
1813 stna %g6, [%g5 + TRAP_ENT_TPC]%asi ! trap_pc = %tpc
1814 rdpr %tstate, %g6
1815 stxa %g6, [%g5 + TRAP_ENT_TSTATE]%asi ! trap_tstate = %tstate
1819 add %g4, INTR_HEAD, %g6
1820 ldn [%g6 + %g7], %g6 ! %g6=cpu->m_cpu.intr_head[pil]
1821 stna %g6, [%g5 + TRAP_ENT_F2]%asi ! trap_f2 = intr_head[pil]
1822 add %g4, INTR_TAIL, %g6
1823 ldn [%g6 + %g7], %g6 ! %g6=cpu->m_cpu.intr_tail[pil]
1824 stna %g6, [%g5 + TRAP_ENT_F3]%asi ! trap_f3 = intr_tail[pil]
1826 GET_TRACE_TICK(%g6, %g7)
1827 stxa %g6, [%g5 + TRAP_ENT_TICK]%asi ! trap_tick = %tick
1828 TRACE_NEXT(%g5, %g6, %g7)
1830 mov 1, %g6 ! %g6 = 1
1831 sll %g6, %g2, %g6 ! %g6 = 1 << pil
1832 or %g1, %g6, %g1 ! %g1 |= (1 << pil), pil mask
1891 add %g4, INTR_TAIL, %g6 ! %g6 = &cpu->m_cpu.intr_tail
1892 ldn [%o0 + %g6], %g1 ! %g1 = cpu->m_cpu.intr_tail[pil]
1895 stn %o1, [%g6 + %o0] ! make intr_vec_t (iv) as new tail
1900 lduh [%g1 + IV_FLAGS], %g6 ! %g6 = ct->iv_flags
1901 and %g6, IV_SOFTINT_MT, %g6 ! %g6 = ct->iv_flags & IV_SOFTINT_MT
1902 brz,pt %g6, 1f ! check for Multi target softint flag
1904 ld [%g4 + CPU_ID], %g6 ! for multi target softint, use cpuid
1905 sll %g6, CPTRSHIFT, %g6 ! calculate offset address from cpuid
1906 add %g3, %g6, %g3 ! %g3 = &ct->iv_xpil_next[cpuid]
1917 add %g4, INTR_HEAD, %g6 ! %g6 = &cpu->m_cpu.intr_head[pil]
1918 stn %o1, [%g6 + %o0] ! cpu->m_cpu.intr_head[pil] = iv