Lines Matching refs:g2
63 ! %g2 - pointer to intr_vec_t (iv)
78 ldn [%g6], %g2 ! %g2 = cpu->m_cpu.intr_head[pil]
79 brnz,pt %g2, 0f ! check list head (iv) is NULL
84 lduh [%g2 + IV_FLAGS], %g7 ! %g7 = iv->iv_flags
87 add %g2, IV_PIL_NEXT, %g7 ! g7% = &iv->iv_pil_next
111 stna %g2, [%g5 + TRAP_ENT_TR]%asi ! trap_tr = first intr_vec
128 lduh [%g2 + IV_FLAGS], %g3 ! %g3 = iv->iv_flags
130 sth %g3, [%g2 + IV_FLAGS] ! clear IV_SOFTINT_PEND flag
139 ! %g2 - pointer to current intr_vec_t (iv),
1627 ! %g2 - pil
1637 CPU_ADDR(%g4, %g2) ! %g4 = cpu
1638 lduh [%g1 + IV_PIL], %g2 ! %g2 = iv->iv_pil
1643 sll %g2, CPTRSHIFT, %g7 ! %g7 = offset to pil entry
1693 stna %g2, [%g5 + TRAP_ENT_F4]%asi ! trap_f4 = pil
1700 sll %g5, %g2, %g5 ! %g5 = 1 << pil
1723 ! %g2 - pil of intr_vec_t
1732 set MAXIVNUM, %g2
1733 cmp %g1, %g2
1735 clr %g2 ! expected in .no_ivintr
1765 CPU_ADDR(%g4, %g2) ! %g4 = cpu
1776 lduh [%g3 + IV_PIL], %g2 ! %g2 = iv->iv_pil
1777 sll %g2, CPTRSHIFT, %g7 ! %g7 = offset to pil entry
1825 stna %g2, [%g5 + TRAP_ENT_F4]%asi ! trap_f4 = pil
1831 sll %g6, %g2, %g6 ! %g6 = 1 << pil
1840 ! no_ivintr: arguments: rp, inum (%g1), pil (%g2 == 0)
1841 mov %g2, %g3
1842 mov %g1, %g2