Lines Matching refs:g1
62 ! %g1 - cpu
72 CPU_ADDR(%g1, %g5) ! %g1 = cpu
76 add %g1, INTR_HEAD, %g6 ! %g6 = &cpu->m_cpu.intr_head
82 mov PTL1_BAD_INTR_VEC, %g1
88 ld [%g1 + CPU_ID], %g3 ! for multi target softint, use cpuid
95 add %g1, INTR_TAIL, %g6 ! %g6 = &cpu->m_cpu.intr_tail
116 add %g1, INTR_HEAD, %g6
119 add %g1, INTR_TAIL, %g6
138 ! %g1 - interrupt handler at TL==0
152 sethi %hi(intr_thread), %g1 ! %g1 = intr_thread
155 or %g1, %lo(intr_thread), %g1
157 sethi %hi(current_thread), %g1 ! %g1 = current_thread
159 or %g1, %lo(current_thread), %g1
1186 andn %g5, PSTATE_IE, %g1
1187 wrpr %g0, %g1, %pstate ! Disable vec interrupts
1475 andn %o0, PSTATE_IE, %g1
1477 wrpr %g0, %g1, %pstate ! disable interrupt
1624 ! %g1 - Pointer to intr_vec_t (iv)
1638 lduh [%g1 + IV_PIL], %g2 ! %g2 = iv->iv_pil
1648 stn %g1, [%g6 + %g7] ! make intr_rec_t (iv) as new tail
1664 stn %g1, [%g3] ! [%g3] = iv, set pil_next field
1670 stn %g1, [%g6 + %g7] ! cpu->m_cpu.intr_head[pil] = iv
1684 stna %g1, [%g5 + TRAP_ENT_TR]%asi ! trap_tr = iv
1685 ldn [%g1 + IV_PIL_NEXT], %g6 !
1719 ! %g1 - inumber
1722 ! %g1 - softint pil mask
1733 cmp %g1, %g2
1745 sll %g1, CPTRSHIFT, %g6 ! %g6 = offset to inum entry in table
1766 mov %g0, %g1 ! %g1 = 0, initialize pil mask to 0
1772 ! %g1 = softint pil mask
1818 stna %g1, [%g5 + TRAP_ENT_F1]%asi ! trap_f1 = pil mask
1832 or %g1, %g6, %g1 ! %g1 |= (1 << pil), pil mask
1836 wr %g1, SET_SOFTINT ! triggered one or more pil softints
1840 ! no_ivintr: arguments: rp, inum (%g1), pil (%g2 == 0)
1842 mov %g1, %g2
1843 set no_ivintr, %g1
1885 CPU_ADDR(%g4, %g1) ! %g4 = cpu
1892 ldn [%o0 + %g6], %g1 ! %g1 = cpu->m_cpu.intr_tail[pil]
1894 brz,pt %g1, 2f ! branch if current tail is NULL
1900 lduh [%g1 + IV_FLAGS], %g6 ! %g6 = ct->iv_flags
1903 add %g1, IV_PIL_NEXT, %g3 ! %g3 = &ct->iv_pil_next