Cross Reference: /illumos-gate/usr/src/uts/sun4/io/px/px

Lines Matching refs:hdlp
478     ddi_intr_handle_impl_t *hdlp, void *result)
484 	    "handle=%p\n", dip, rdip, intr_op, hdlp);
495 		*(int *)result = hdlp->ih_scratch1;
500 		*(int *)result = hdlp->ih_pri ?
501 		    hdlp->ih_pri : pci_class_to_pil(rdip);
506 		ret = px_add_intx_intr(dip, rdip, hdlp);
509 		ret = px_rem_intx_intr(dip, rdip, hdlp);
512 		ret = px_ib_get_intr_target(px_p, hdlp->ih_vector,
519 		ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum,
520 		    hdlp->ih_vector, hdlp->ih_pri, PX_INTR_STATE_ENABLE, 0, 0);
523 		ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum,
524 		    hdlp->ih_vector, hdlp->ih_pri, PX_INTR_STATE_DISABLE, 0, 0);
550     ddi_intr_handle_impl_t *hdlp, void *result)
563 	    "handle=%p\n", dip, rdip, intr_op, hdlp);
566 	if ((hdlp->ih_cap & DDI_INTR_FLAG_MSI64) && msi_state_p->msi_addr64) {
576 	(void) px_msi_get_msinum(px_p, hdlp->ih_dip,
577 	    (hdlp->ih_flags & DDI_INTR_MSIX_DUP) ? hdlp->ih_main->ih_inum :
578 	    hdlp->ih_inum, &msi_num);
582 		ret = pci_msi_get_cap(rdip, hdlp->ih_type, (int *)result);
593 		if ((ret = px_msi_alloc(px_p, rdip, hdlp->ih_type,
594 		    hdlp->ih_inum, hdlp->ih_scratch1,
595 		    (uintptr_t)hdlp->ih_scratch2,
599 			    "count 0x%x\n", rdip, hdlp->ih_type, hdlp->ih_inum,
600 			    hdlp->ih_scratch1);
605 		if ((hdlp->ih_type == DDI_INTR_TYPE_MSIX) &&
616 			    hdlp->ih_inum);
618 			(void) px_msi_free(px_p, rdip, hdlp->ih_inum,
619 			    hdlp->ih_scratch1);
626 		(void) pci_msi_unconfigure(rdip, hdlp->ih_type, hdlp->ih_inum);
628 		if (hdlp->ih_type == DDI_INTR_TYPE_MSI)
631 		if (hdlp->ih_flags & DDI_INTR_MSIX_DUP)
634 		if (((i_ddi_intr_get_current_nintrs(hdlp->ih_dip) - 1) == 0) &&
640 		(void) px_msi_free(px_p, rdip, hdlp->ih_inum,
641 		    hdlp->ih_scratch1);
644 		*(int *)result = hdlp->ih_pri ?
645 		    hdlp->ih_pri : pci_class_to_pil(rdip);
650 		if ((ret = px_add_msiq_intr(dip, rdip, hdlp,
662 			    hdlp, msiq_rec_type, msi_num, msiq_id);
669 			    hdlp, msiq_rec_type, msi_num, msiq_id);
677 		ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum,
678 		    px_msiqid_to_devino(px_p, msiq_id), hdlp->ih_pri,
684 		    "new_vector: %x\n", hdlp->ih_inum, hdlp->ih_scratch1);
686 		ret = pci_msix_dup(hdlp->ih_dip, hdlp->ih_inum,
687 		    hdlp->ih_scratch1);
695 		    hdlp->ih_inum, px_msiqid_to_devino(px_p, msiq_id),
696 		    hdlp->ih_pri, PX_INTR_STATE_DISABLE, msiq_rec_type,
709 		    hdlp, msiq_rec_type, msi_num, msiq_id);
721 		ret = px_ib_set_msix_target(px_p, hdlp, msi_num,
731 		if ((pci_is_msi_enabled(rdip, hdlp->ih_type) != DDI_SUCCESS) ||
732 		    (hdlp->ih_type == DDI_INTR_TYPE_MSIX)) {
733 			nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip);
735 			if ((ret = pci_msi_configure(rdip, hdlp->ih_type,
736 			    nintrs, hdlp->ih_inum, msi_addr,
737 			    hdlp->ih_type == DDI_INTR_TYPE_MSIX ?
743 				    hdlp->ih_type)) != DDI_SUCCESS)
748 		if ((ret = pci_msi_clr_mask(rdip, hdlp->ih_type,
749 		    hdlp->ih_inum)) != DDI_SUCCESS)
754 		if ((ret = pci_msi_set_mask(rdip, hdlp->ih_type,
755 		    hdlp->ih_inum)) != DDI_SUCCESS)
766 		if ((ret = pci_msi_disable_mode(rdip, hdlp->ih_type))
772 		nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip);
774 		if ((ret = pci_msi_configure(rdip, hdlp->ih_type,
775 		    nintrs, hdlp->ih_inum, msi_addr,
779 		ret = pci_msi_enable_mode(rdip, hdlp->ih_type);
782 		ret = pci_msi_disable_mode(rdip, hdlp->ih_type);
785 		ret = pci_msi_set_mask(rdip, hdlp->ih_type, hdlp->ih_inum);
788 		ret = pci_msi_clr_mask(rdip, hdlp->ih_type, hdlp->ih_inum);
791 		ret = pci_msi_get_pending(rdip, hdlp->ih_type,
792 		    hdlp->ih_inum, (int *)result);
795 		ret = pci_msi_get_nintrs(rdip, hdlp->ih_type, (int *)result);
799 		ret = pci_msi_get_nintrs(rdip, hdlp->ih_type, (int *)result);
942     ddi_intr_handle_impl_t *hdlp)
954 	ino = hdlp->ih_vector;
958 	    ddi_get_instance(rdip), ino, hdlp->ih_cb_func,
959 	    hdlp->ih_cb_arg1, hdlp->ih_cb_arg2);
961 	ih_p = px_ib_alloc_ih(rdip, hdlp->ih_inum,
962 	    hdlp->ih_cb_func, hdlp->ih_cb_arg1, hdlp->ih_cb_arg2, 0, 0);
969 	if (hdlp->ih_pri == 0)
970 		hdlp->ih_pri = pci_class_to_pil(rdip);
973 	if (ino_p && (ipil_p = px_ib_ino_locate_ipil(ino_p, hdlp->ih_pri))) {
974 		if (px_ib_intr_locate_ih(ipil_p, rdip, hdlp->ih_inum, 0, 0)) {
976 			    "dup intr #%d\n", hdlp->ih_inum);
982 		/* Save mondo value in hdlp */
983 		hdlp->ih_vector = ino_p->ino_sysino;
1018 	ipil_p = px_ib_new_ino_pil(ib_p, ino, hdlp->ih_pri, ih_p);
1021 	/* Save mondo value in hdlp */
1022 	hdlp->ih_vector = ino_p->ino_sysino;
1025 	    hdlp->ih_pri, hdlp->ih_vector);
1027 	DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp,
1030 	ret = i_ddi_add_ivintr(hdlp);
1036 	DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, ih_p->ih_handler,
1043 	ipil_p->ipil_pil = hdlp->ih_pri;
1058 	hdlp->ih_target = ino_p->ino_cpuid;
1071 	    ino_p->ino_sysino, hdlp->ih_pri);
1084 	    "pil=%x\n", ino_p->ino_sysino, hdlp->ih_pri);
1097     ddi_intr_handle_impl_t *hdlp)
1108 	ino = hdlp->ih_vector;
1116 	ipil_p = px_ib_ino_locate_ipil(ino_p, hdlp->ih_pri);
1117 	ih_p = px_ib_intr_locate_ih(ipil_p, rdip, hdlp->ih_inum, 0, 0);
1130 		hdlp->ih_vector = ino_p->ino_sysino;
1131 		i_ddi_rem_ivintr(hdlp);
1155     ddi_intr_handle_impl_t *hdlp, msiq_rec_type_t rec_type,
1170 	    ddi_get_instance(rdip), hdlp->ih_cb_func, hdlp->ih_cb_arg1,
1171 	    hdlp->ih_cb_arg2, cpu_id);
1173 	ih_p = px_ib_alloc_ih(rdip, hdlp->ih_inum, hdlp->ih_cb_func,
1174 	    hdlp->ih_cb_arg1, hdlp->ih_cb_arg2, rec_type, msg_code);
1193 	if (hdlp->ih_pri == 0)
1194 		hdlp->ih_pri = pci_class_to_pil(rdip);
1197 	if (ino_p && (ipil_p = px_ib_ino_locate_ipil(ino_p, hdlp->ih_pri))) {
1199 		    hdlp->ih_inum, rec_type, msg_code)) {
1201 			    "dup intr #%d\n", hdlp->ih_inum);
1207 		/* Save mondo value in hdlp */
1208 		hdlp->ih_vector = ino_p->ino_sysino;
1217 	ipil_p = px_ib_new_ino_pil(ib_p, ino, hdlp->ih_pri, ih_p);
1223 	/* Save mondo value in hdlp */
1224 	hdlp->ih_vector = ino_p->ino_sysino;
1227 	    hdlp->ih_pri, hdlp->ih_vector);
1229 	DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp,
1232 	ret = i_ddi_add_ivintr(hdlp);
1238 	DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, ih_p->ih_handler,
1245 	ipil_p->ipil_pil = hdlp->ih_pri;
1261 	hdlp->ih_target = ino_p->ino_cpuid;
1274 	    ino_p->ino_sysino, hdlp->ih_pri);
1289 	    ino_p->ino_sysino, hdlp->ih_pri);
1301     ddi_intr_handle_impl_t *hdlp, msiq_rec_type_t rec_type,
1319 	ipil_p = px_ib_ino_locate_ipil(ino_p, hdlp->ih_pri);
1320 	ih_p = px_ib_intr_locate_ih(ipil_p, rdip, hdlp->ih_inum, rec_type,
1334 		hdlp->ih_vector = ino_p->ino_sysino;
1335 		i_ddi_rem_ivintr(hdlp);