Lines Matching refs:hdlp
921 px_ib_set_msix_target(px_t *px_p, ddi_intr_handle_impl_t *hdlp,
927 dev_info_t *rdip = hdlp->ih_dip;
946 if ((hdlp->ih_cap & DDI_INTR_FLAG_MSI64) && msi_state_p->msi_addr64) {
996 if ((ret = px_add_msiq_intr(dip, rdip, hdlp,
1010 hdlp, msiq_rec_type, msi_num, msiq_id);
1015 if ((ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum,
1016 px_msiqid_to_devino(px_p, msiq_id), hdlp->ih_pri,
1021 hdlp, msiq_rec_type, msi_num, msiq_id);
1043 hdlp->ih_pri), rdip, hdlp->ih_inum, msiq_rec_type, msi_num);
1046 ih_p = px_ib_intr_locate_ih(px_ib_ino_locate_ipil(ino_p, hdlp->ih_pri),
1047 rdip, hdlp->ih_inum, msiq_rec_type, msi_num);
1052 hdlp, msiq_rec_type, msi_num, msiq_id);
1085 hdlp, msiq_rec_type, msi_num, old_msiq_id);
1169 ddi_intr_handle_impl_t *hdlp)
1193 hdlp->ih_dip = ih_p->ih_dip;
1194 hdlp->ih_inum = ih_p->ih_inum;
1195 hdlp->ih_cb_func = ih_p->ih_handler;
1196 hdlp->ih_cb_arg1 = ih_p->ih_handler_arg1;
1197 hdlp->ih_cb_arg2 = ih_p->ih_handler_arg2;
1199 hdlp->ih_cap = DDI_INTR_FLAG_MSI64;
1200 hdlp->ih_pri = ipil_p->ipil_pil;
1201 hdlp->ih_ver = DDI_INTR_VERSION;