Lines Matching refs:dip
52 static int px_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
53 static int px_detach(dev_info_t *dip, ddi_detach_cmd_t cmd);
56 static int px_info(dev_info_t *dip, ddi_info_cmd_t infocmd,
59 static int px_pwr_setup(dev_info_t *dip);
60 static void px_pwr_teardown(dev_info_t *dip);
191 px_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result)
224 px_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
227 int instance = DIP_TO_INST(dip);
235 DBG(DBG_ATTACH, dip, "DDI_ATTACH\n");
246 ddi_driver_name(dip), instance);
250 px_p->px_dip = dip;
254 (void) ddi_prop_update_string(DDI_DEV_T_NONE, dip,
258 px_dbg_attach(dip, &px_p->px_dbg_hdl);
259 pcie_rc_init_bus(dip);
265 if (px_get_props(px_p, dip) == DDI_FAILURE)
268 if (px_lib_dev_init(dip, &dev_hdl) != DDI_SUCCESS)
318 if (px_lib_hotplug_init(dip, (void *)®ops) == DDI_SUCCESS) {
319 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
326 if (pcie_init(dip, (caddr_t)®ops) != DDI_SUCCESS)
329 (void) pcie_hpintr_enable(dip);
331 if (pxtool_init(dip) != DDI_SUCCESS)
339 if (pwr_common_setup(dip) != DDI_SUCCESS) {
340 DBG(DBG_PWR, dip, "pwr_common_setup failed\n");
341 } else if (px_pwr_setup(dip) != DDI_SUCCESS) {
342 DBG(DBG_PWR, dip, "px_pwr_setup failed \n");
343 pwr_common_teardown(dip);
355 (void) px_lib_fabric_sync(dip);
357 ddi_report_dev(dip);
365 bus_p = PCIE_DIP2BUS(dip);
366 bus_p->bus_cfgacc_base = px_lib_get_cfgacc_base(dip);
377 pcie_fab_init_bus(dip, PCIE_BUS_ALL);
379 DBG(DBG_ATTACH, dip, "attach success\n");
383 (void) pcie_hpintr_disable(dip);
384 (void) pcie_uninit(dip);
386 (void) px_lib_hotplug_uninit(dip);
402 if (px_lib_dev_fini(dip) != DDI_SUCCESS) {
403 DBG(DBG_ATTACH, dip, "px_lib_dev_fini failed\n");
408 pcie_rc_fini_bus(dip);
409 px_dbg_detach(dip, &px_p->px_dbg_hdl);
417 DBG(DBG_ATTACH, dip, "DDI_RESUME\n");
432 px_lib_resume(dip);
433 (void) pcie_pwr_resume(dip);
440 DBG(DBG_ATTACH, dip, "unsupported attach op\n");
453 px_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
455 int instance = ddi_get_instance(dip);
457 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
464 DBG(DBG_DETACH, dip, "Instance not attached\n");
472 DBG(DBG_DETACH, dip, "DDI_DETACH\n");
479 (void) pcie_hpintr_disable(dip);
482 (void) px_lib_hotplug_uninit(dip);
484 if (pcie_uninit(dip) != DDI_SUCCESS) {
490 pcie_fab_fini_bus(dip, PCIE_BUS_ALL);
499 pxtool_uninit(dip);
504 px_pwr_teardown(dip);
505 pwr_common_teardown(dip);
510 if (px_lib_dev_fini(dip) != DDI_SUCCESS) {
511 DBG(DBG_DETACH, dip, "px_lib_dev_fini failed\n");
519 pcie_rc_fini_bus(dip);
520 px_dbg_detach(dip, &px_p->px_dbg_hdl);
530 if (pcie_pwr_suspend(dip) != DDI_SUCCESS) {
534 if ((ret = px_lib_suspend(dip)) == DDI_SUCCESS)
541 DBG(DBG_DETACH, dip, "unsupported detach op\n");
590 dev_info_t *dip = px_p->px_dip;
593 if (px_lib_intr_devino_to_sysino(dip,
597 fault_p->px_fh_dip = dip;
610 px_pwr_setup(dev_info_t *dip)
613 int instance = ddi_get_instance(dip);
617 ASSERT(PCIE_PMINFO(dip));
618 pwr_p = PCIE_NEXUS_PMINFO(dip);
625 if (!ddi_prop_exists(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS,
627 if (ddi_prop_create(DDI_DEV_T_NONE, dip, DDI_PROP_CANSLEEP,
629 DBG(DBG_PWR, dip, "can't create kernel ioctl prop\n");
645 hdl.ih_dip = dip;
650 if (px_add_msiq_intr(dip, dip, &hdl, MSG_REC,
653 DBG(DBG_PWR, dip, "px_pwr_setup: couldn't add "
657 px_lib_msg_setmsiq(dip, PCIE_PME_ACK_MSG, px_p->px_pm_msiq_id);
658 px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_VALID);
663 DBG(DBG_PWR, dip, "px_pwr_setup: PME_TO_ACK update interrupt"
671 px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_INVALID);
672 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG,
685 px_pwr_teardown(dev_info_t *dip)
687 int instance = ddi_get_instance(dip);
691 if (!PCIE_PMINFO(dip) || !PCIE_NEXUS_PMINFO(dip))
698 hdl.ih_dip = dip;
701 px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_INVALID);
702 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG,
727 px_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp,
730 px_t *px_p = DIP_TO_STATE(dip);
736 DBG(DBG_MAP, dip, "rdip=%s%d:",
749 DBG(DBG_MAP | DBG_CONT, dip, " r#=%x", r_no);
765 DBG(DBG_MAP | DBG_CONT, dip, "\n");
784 rval = px_lib_map_vconfig(dip, mp, off, rp, addrp);
796 if (rval = px_reloc_reg(dip, rdip, px_p, rp))
811 rval = ddi_map(dip, &p_mapreq, 0, 0, addrp);
839 px_dma_setup(dev_info_t *dip, dev_info_t *rdip, ddi_dma_req_t *dmareq,
842 px_t *px_p = DIP_TO_STATE(dip);
847 DBG(DBG_DMA_MAP, dip, "mapping - rdip=%s%d type=%s\n",
851 if (!(mp = px_dma_lmts2hdl(dip, rdip, mmu_p, dmareq)))
889 px_dump_dma_handle(DBG_DMA_MAP, dip, mp);
896 (void) px_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp);
905 px_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp,
908 px_t *px_p = DIP_TO_STATE(dip);
912 DBG(DBG_DMA_ALLOCH, dip, "rdip=%s%d\n",
918 if (!(mp = px_dma_allocmp(dip, rdip, waitfp, arg)))
926 DBG(DBG_DMA_ALLOCH, dip, "mp=%p\n", mp);
930 px_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp);
944 px_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle)
946 DBG(DBG_DMA_FREEH, dip, "rdip=%s%d mp=%p\n",
951 DBG(DBG_DMA_FREEH, dip, "run handle callback\n");
962 px_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip,
966 px_t *px_p = DIP_TO_STATE(dip);
971 DBG(DBG_DMA_BINDH, dip, "rdip=%s%d mp=%p dmareq=%p\n",
1016 DBG(DBG_DMA_BINDH, dip, "cookie %" PRIx64 "+%x\n",
1018 px_dump_dma_handle(DBG_DMA_MAP, dip, mp);
1038 px_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle)
1041 px_t *px_p = DIP_TO_STATE(dip);
1044 DBG(DBG_DMA_UNBINDH, dip, "rdip=%s%d, mp=%p\n",
1047 DBG(DBG_DMA_UNBINDH, dip, "handle not inuse\n");
1073 DBG(DBG_DMA_UNBINDH, dip, "run dvma callback\n");
1077 DBG(DBG_DMA_UNBINDH, dip, "run handle callback\n");
1089 px_dma_win(dev_info_t *dip, dev_info_t *rdip,
1096 DBG(DBG_DMA_WIN, dip, "rdip=%s%d\n",
1099 px_dump_dma_handle(DBG_DMA_WIN, dip, mp);
1101 DBG(DBG_DMA_WIN, dip, "%x out of range\n", win);
1108 px_t *px_p = DIP_TO_STATE(dip);
1149 DBG(DBG_DMA_WIN, dip,
1189 px_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle,
1196 DBG(DBG_DMA_CTL, dip, "%s: rdip=%s%d\n", px_dmactl_str[cmd],
1202 (void) px_dma_unbindhdl(dip, rdip, handle);
1203 (void) px_dma_freehdl(dip, rdip, handle);
1206 px_t *px_p = DIP_TO_STATE(dip);
1207 return (px_fdvma_reserve(dip, rdip, px_p,
1211 px_t *px_p = DIP_TO_STATE(dip);
1212 return (px_fdvma_release(dip, px_p, mp));
1220 return (px_dvma_ctl(dip, rdip, mp, cmd, offp, lenp, objp,
1224 return (px_dma_ctl(dip, rdip, mp, cmd, offp, lenp, objp,
1252 px_ctlops(dev_info_t *dip, dev_info_t *rdip,
1255 px_t *px_p = DIP_TO_STATE(dip);
1267 if (!pcie_is_child(dip, rdip))
1274 DBG(DBG_PWR, dip, "PRE_ATTACH for %s@%d\n",
1277 return (pcie_pm_hold(dip));
1280 DBG(DBG_PWR, dip, "PRE_RESUME for %s@%d\n",
1289 DBG(DBG_PWR, dip, "POST_ATTACH for %s@%d\n",
1300 return (pcie_pm_remove_child(dip, rdip));
1315 if (!pcie_is_child(dip, rdip))
1323 DBG(DBG_PWR, dip, "POST_DETACH for %s@%d\n",
1326 return (pcie_pm_remove_child(dip, rdip));
1338 if (ddi_get_parent(rdip) == dip)
1360 return (px_lib_ctlops_poke(dip, rdip,
1364 return (px_lib_ctlops_peek(dip, rdip,
1375 DBG(DBG_CTLOPS, dip, "passing request to parent: rdip=%s%d\n",
1377 return (ddi_ctlops(dip, rdip, op, arg, result));
1382 px_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
1386 px_t *px_p = DIP_TO_STATE(dip);
1388 DBG(DBG_INTROPS, dip, "px_intr_ops: rdip=%s%d\n",
1418 ret = px_intx_ops(dip, rdip, intr_op, hdlp, result);
1422 ret = px_msix_ops(dip, rdip, intr_op, hdlp, result);
1435 dev_info_t *dip;
1439 dip = px_p->px_dip;
1440 bus_p = PCIE_DIP2BUS(dip);
1444 if (pcie_root_port(dip) == DDI_FAILURE) {
1445 if (px_lib_get_root_complex_mps(px_p, dip,
1448 DBG(DBG_MPS, dip, "MPS: Can not get RC MPS\n");
1452 DBG(DBG_MPS, dip, "MPS: Root Complex MPS Cap of = %x\n",
1458 (void) pcie_get_fabric_mps(dip, ddi_get_child(dip),
1463 (void) px_lib_set_root_complex_mps(px_p, dip, bus_p->bus_mps);
1465 DBG(DBG_MPS, dip, "MPS: Root Complex MPS Set to = %x\n",