110  * 1275 "bus-range" property of a PCI Bus node.
155 	uint_t		highest_bus;	/* Highest bus seen on the probe */
395 	{ 0xc01, "access-bus" },
704  * all its children) on the given bus. It is called when
714 	uint_t bus;
732 	 * "bus" specified.
736 	    "bus-range", (caddr_t)&pci_bus_range, &len) != DDI_SUCCESS) {
737 		DEBUG0("no bus-range property\n");
741 	bus = pci_bus_range.lo; /* primary bus number of this bus node */
756 		    bus, trans_device, func & 7);
761 		switch (rv = pcicfg_fcode_probe(devi, bus, trans_device,
765 				    "bus [0x%x] device [0x%x]\n",
766 				    bus, trans_device);
769 				DEBUG3("no device : bus "
771 				    bus, trans_device, func & 7);
786 				DEBUG3("configure: bus => [%d] "
788 				    bus, trans_device, func & 7);
907 pcicfg_configure_ntbridge(dev_info_t *new_device, uint_t bus, uint_t device)
952 		DEBUG0("ntbridge: Failed to get a bus number\n");
956 	DEBUG1("ntbridge bus range start  ->[%d]\n", next_bus);
966 	    "bus-range", bus_range, 2) != DDI_SUCCESS) {
967 		DEBUG0("Cannot set ntbridge bus-range property");
1000 	/* Probe devices on 2nd bus */
1063 	DEBUG1("ntbridge: finish probing 2nd bus, rc=%d\n", rc);
1069 		uint_t			*bus;
1073 		    DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus,
1075 			DEBUG0("Failed to read bus-range property\n");
1080 		DEBUG2("Need to free bus [%d] range [%d]\n",
1081 		    bus[0], bus[1] - bus[0] + 1);
1084 		    (uint64_t)bus[0], (uint64_t)(bus[1] - bus[0] + 1),
1086 			DEBUG0("Failed to free a bus number\n");
1091 			kmem_free((caddr_t)bus, k);
1111 		kmem_free((caddr_t)bus, k);
1258 	    "bus-range", (caddr_t)&bus_range, (int *)&len) != DDI_SUCCESS) {
1259 		DEBUG0("no bus-range property\n");
1263 	new_bus_range[0] = bus_range.lo;	/* primary bus number */
1264 	if (entry->highest_bus) {	/* secondary bus number */
1267 			    "ntbridge bus range invalid !(%d,%d)\n",
1277 	DEBUG2("ntbridge: bus range lo=%x, hi=%x\n",
1281 	    "bus-range", new_bus_range, 2) != DDI_SUCCESS) {
1282 		DEBUG0("Failed to set bus-range property");
1327 	int 		len, bus;
1334 	    "bus-range", (caddr_t)&pci_bus_range, &len) != DDI_SUCCESS) {
1335 		DEBUG0("no bus-range property\n");
1339 	bus = pci_bus_range.lo; /* primary bus number of this bus node */
1348 	if (pcicfg_add_config_reg(new_ntbridgechild, bus, devno, 0)
1384 	uint_t			*bus;
1400 	    DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus,
1402 		DEBUG0("ntbridge: Failed to read bus-range property\n");
1406 	DEBUG2("ntbridge: Need to free bus [%d] range [%d]\n",
1407 	    bus[0], bus[1] - bus[0] + 1);
1410 	    (uint64_t)bus[0], (uint64_t)(bus[1] - bus[0] + 1),
1412 		DEBUG0("ntbridge: Failed to free a bus number\n");
1416 		kmem_free((caddr_t)bus, k);
1424 	kmem_free((caddr_t)bus, k);
1926 		    "bus-range", bus_range, 2) != DDI_SUCCESS) {
1927 			DEBUG0("Failed to set bus-range property");
2616 	 * If its a bridge - just record the highest bus seen
2813 	uint_t			*bus;
2889 	    DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus,
2891 		DEBUG0("Failed to read bus-range property\n");
2895 	DEBUG2("Need to free bus [%d] range [%d]\n",
2896 	    bus[0], bus[1] - bus[0] + 1);
2899 	    (uint64_t)bus[0], (uint64_t)(bus[1] - bus[0] + 1),
2902 		DEBUG0("Failed to free a bus number\n");
2907 	kmem_free((caddr_t)bus, k);
3384 	 * Enable memory, IO, and bus mastership
3583 	 * Create primary-bus and secondary-bus properties to be used
3584 	 * to restore bus numbers in the pcicfg_setup_bridge() routine.
3588 		    "primary-bus", pbus)) != DDI_SUCCESS) {
3592 		    "secondary-bus", sbus)) != DDI_SUCCESS) {
3772  * Program the bus numbers into the bridge
3779 	DEBUG3("Setting bridge bus-range %d,%d,%d\n", primary, secondary,
3782 	 * Primary bus#
3787 	 * Secondary bus#
3792 	 * Subordinate bus#
3807 	 * The highest bus seen during probing is the max-subordinate bus
3814 	 * will be reset by the below secondary bus reset which
3815 	 * will clear the bus numbers assumed to be programmed in
3821 		    DDI_PROP_DONTPASS, "primary-bus", -1);
3823 		    DDI_PROP_DONTPASS, "secondary-bus", -1);
3836 	 * Reset the secondary bus
4006 pcicfg_probe_children(dev_info_t *parent, uint_t bus, uint_t device,
4031 	if (pcicfg_add_config_reg(new_child, bus,
4050 		(void) pcie_init_bus(new_child, PCI_GETBDF(bus, device, func),
4108 		DEBUG3("--Bridge found bus [0x%x] device"
4109 		    "[0x%x] func [0x%x]\n", bus, device, func);
4116 		    bus, highest_bus, is_pcie) != PCICFG_SUCCESS) {
4123 		DEBUG3("--Leaf device found bus [0x%x] device"
4125 		    bus, device, func);
4277 pcicfg_fcode_probe(dev_info_t *parent, uint_t bus, uint_t device,
4341 	if (pcicfg_add_config_reg(new_child, bus,
4356 	p.pci_phys_hi = PCICFG_MAKE_REG_HIGH(bus, device, func, 0);
4376 	 * a bus error will not cause a panic.
4388 		(void) pcie_init_bus(new_child, PCI_GETBDF(bus, device, func),
4447 		DEBUG3("--Bridge found bus [0x%x] device"
4448 		    "[0x%x] func [0x%x]\n", bus, device, func);
4455 		    bus, highest_bus, is_pcie)) != PCICFG_SUCCESS)
4460 		DEBUG3("--Leaf device found bus [0x%x] device"
4462 		    bus, device, func);
4507 				    bus, device, func, request, &p)
4521 				(void) pcicfg_load_fcode(new_child, bus, device,
4557 			 * Fill in the bus specific arguments. For
4561 			    PCICFG_MAKE_REG_HIGH(bus, device, func, 0);
4689 			ret = pcicfg_probe_children(parent, bus, device, func,
4712 			 * header which is the side facing the host bus.
4733 				    bus, device);
4738 				 * probed entry. The bus resource allocation
4892 pcicfg_probe_bridge(dev_info_t *new_child, ddi_acc_handle_t h, uint_t bus,
4945 			DEBUG0("NDI_RA_PARTIAL_REQ returned for bus range\n");
4948 			    "Failed to allocate bus range for bridge\n");
4963 	 * Put available bus range into the pool.
4975 	DEBUG1("NEW bus found  ->[%d]\n", new_bus);
4977 	/* Keep track of highest bus for subordinate bus programming */
5070 	pcicfg_set_bus_numbers(h, bus, new_bus, max_bus);
5073 	 * Setup "bus-range" property before onlining the bridge.
5079 	    "bus-range", bus_range, 2) != DDI_SUCCESS) {
5080 		DEBUG0("Failed to set bus-range property");
5085 	 * Reset the secondary bus
5216 	 * Set bus properties
5219 	    (int)bus, (int)new_bus) != PCICFG_SUCCESS) {
5261 					DEBUG3("No Device at bus [0x%x]"
5269 					DEBUG3("Failed to configure bus "
5519 		 * Give back unused bus numbers
5527 	 * Set bus numbers to ranges encountered during scan
5529 	pcicfg_set_bus_numbers(h, bus, new_bus, *highest_bus);
5537 	    "bus-range", bus_range, 2) != DDI_SUCCESS) {
5538 		DEBUG0("Failed to set bus-range property");
5744 	uint_t bus, uint_t device, uint_t func)
5748 	reg[0] = PCICFG_MAKE_REG_HIGH(bus, device, func, 0);
5785 pcicfg_load_fcode(dev_info_t *dip, uint_t bus, uint_t device, uint_t func,
5805 	    "bus %x device =%x func=%x rom_paddr=%lx\n",
5806 	    bus, device, func, rom_paddr);
5817 	p.pci_phys_hi = PCI_ADDR_MEM32 | PCICFG_MAKE_REG_HIGH(bus, device,
5999 pcicfg_fcode_assign_bars(ddi_acc_handle_t h, dev_info_t *dip, uint_t bus,
6036 		hiword = PCICFG_MAKE_REG_HIGH(bus, device, func, i);
6125 	phys_spec.pci_phys_hi = PCICFG_MAKE_REG_HIGH(bus, device, func, \
6828 	char *bus;
6836 		    DDI_PROP_DONTPASS, "device_type", &bus) !=
6840 		if (strcmp(bus, "pciex") == 0)
6843 		ddi_prop_free(bus);

Indexes created Tue Jul 24 14:28:13 CEST 2018