Cross Reference: /illumos-gate/usr/src/uts/sun4/io/pcicfg.c

Lines Matching defs:phys_spec
6011 	pci_regspec_t phys_spec;
6034 		 * Build the phys_spec for this BAR
6055 		phys_spec.pci_phys_hi = hiword;
6056 		phys_spec.pci_phys_mid = 0;
6057 		phys_spec.pci_phys_low = 0;
6058 		phys_spec.pci_size_hi = 0;
6059 		phys_spec.pci_size_low = size;
6067 		if (pcicfg_alloc_resource(dip, phys_spec)) {
6125 	phys_spec.pci_phys_hi = PCICFG_MAKE_REG_HIGH(bus, device, func, \
6128 		phys_spec.pci_phys_hi |= PCI_REG_PF_M;
6129 	phys_spec.pci_phys_mid = 0;
6130 	phys_spec.pci_phys_low = PCICFG_LOADDR(mem_answer);
6131 	phys_spec.pci_size_hi = 0;
6132 	phys_spec.pci_size_low = size;
6134 	if (pcicfg_update_assigned_prop(dip, &phys_spec)
6144 	*rom_regspec = phys_spec;
6349 pcicfg_alloc_resource(dev_info_t *dip, pci_regspec_t phys_spec)
6375 			if (assigned[i].pci_phys_hi == phys_spec.pci_phys_hi) {
6387 	config.pci_phys_hi = PCI_CONF_ADDR_MASK & phys_spec.pci_phys_hi;
6408 	 * Use size stored in phys_spec parameter.
6410 	request.ra_len = phys_spec.pci_size_low;
6412 	offset = PCI_REG_REG_G(phys_spec.pci_phys_hi);
6416 	if (PCI_REG_REG_G(phys_spec.pci_phys_hi) == PCI_CONF_ROM) {
6439 		phys_spec.pci_phys_low = PCICFG_LOADDR(answer);
6440 		phys_spec.pci_phys_mid = PCICFG_HIADDR(answer);
6443 		switch (PCI_REG_ADDR_G(phys_spec.pci_phys_hi)) {
6470 			phys_spec.pci_phys_low = PCICFG_LOADDR(answer);
6471 			phys_spec.pci_phys_mid = PCICFG_HIADDR(answer);
6476 			phys_spec.pci_phys_hi ^= PCI_ADDR_MEM64 ^
6503 			phys_spec.pci_phys_low = PCICFG_LOADDR(answer);
6525 			phys_spec.pci_phys_low = PCICFG_LOADDR(answer);
6540 	DEBUG1("updating assigned-addresss for %x\n",  phys_spec.pci_phys_hi);
6542 	if (pcicfg_update_assigned_prop(dip, &phys_spec)) {
6553 pcicfg_free_resource(dev_info_t *dip, pci_regspec_t phys_spec,
6566 	config.pci_phys_hi = PCI_CONF_ADDR_MASK & phys_spec.pci_phys_hi;
6583 	offset = PCI_REG_REG_G(phys_spec.pci_phys_hi);
6588 	 * Use size stored in phys_spec parameter.
6590 	l = phys_spec.pci_size_low;
6592 	if (PCI_REG_REG_G(phys_spec.pci_phys_hi) == PCI_CONF_ROM) {
6595 		if (ndi_ra_free(ddi_get_parent(dip), phys_spec.pci_phys_low,
6608 		switch (PCI_REG_ADDR_G(phys_spec.pci_phys_hi)) {
6614 			    PCICFG_LADDR(phys_spec.pci_phys_low,
6615 			    phys_spec.pci_phys_mid),
6627 			    phys_spec.pci_phys_low,
6648 	DEBUG1("updating assigned-addresss for %x\n", phys_spec.pci_phys_hi);
6650 	if (pcicfg_remove_assigned_prop(dip, &phys_spec)) {
6731 pcicfg_map_phys(dev_info_t *dip, pci_regspec_t *phys_spec,
6750 	mr.map_obj.rp = (struct regspec *)phys_spec;