Lines Matching defs:entry
703 * This entry point is called to configure a device (and
1068 pcicfg_phdl_t *entry = pcicfg_find_phdl(new_device);
1104 entry->memory_len = 0;
1105 entry->io_len = 0;
1236 pcicfg_phdl_t *entry;
1243 entry = pcicfg_find_phdl(dip);
1244 ASSERT(entry);
1250 range[1].child_lo = range[1].parent_lo = (uint32_t)entry->memory_base;
1254 range[0].child_lo = range[0].parent_lo = (uint32_t)entry->io_base;
1264 if (entry->highest_bus) { /* secondary bus number */
1265 if (entry->highest_bus < bus_range.lo) {
1268 bus_range.lo, entry->highest_bus);
1269 new_bus_range[1] = bus_range.lo + entry->highest_bus;
1272 new_bus_range[1] = entry->highest_bus;
1283 entry->error = PCICFG_FAILURE;
1290 unused = pcicfg_unused_space(&entry->io_hole, &len);
1296 range[0].size_lo = entry->io_len;
1299 entry->error = PCICFG_FAILURE;
1306 unused = pcicfg_unused_space(&entry->mem_hole, &len);
1312 range[1].size_lo = entry->memory_len;
1315 entry->error = PCICFG_FAILURE;
1383 pcicfg_phdl_t *entry = pcicfg_find_phdl(dip);
1387 if (entry->memory_len)
1390 entry->memory_len);
1393 if (entry->io_len)
1396 entry->io_len);
1430 entry->memory_len = 0;
1431 entry->io_len = 0;
1721 pcicfg_phdl_t *entry;
1723 for (entry = pcicfg_phdl_list; entry != NULL; entry = entry->next) {
1724 if (entry->dip == dip) {
1726 return (entry);
1732 * Did'nt find entry - create one
1757 pcicfg_phdl_t *entry;
1761 for (entry = pcicfg_phdl_list; entry != NULL; follow = entry,
1762 entry = entry->next) {
1763 if (entry->dip == dip) {
1764 if (entry == pcicfg_phdl_list) {
1765 pcicfg_phdl_list = entry->next;
1767 follow->next = entry->next;
1770 * If this entry has any allocated memory
1774 if (entry->memory_len > 0) {
1776 entry->memory_base,
1777 entry->memory_len,
1780 pcicfg_free_hole(&entry->mem_hole);
1782 if (entry->io_len > 0) {
1784 entry->io_base,
1785 entry->io_len,
1788 pcicfg_free_hole(&entry->io_hole);
1791 * Destroy this entry
1793 kmem_free((caddr_t)entry, sizeof (pcicfg_phdl_t));
1800 * Did'nt find the entry
1811 pcicfg_phdl_t *entry;
1848 entry = (pcicfg_phdl_t *)phdl;
1850 entry->memory_len = entry->io_len = 0;
1853 * Free up the "entry" structure.
1880 pcicfg_phdl_t *entry = (pcicfg_phdl_t *)hdl;
1884 if (entry == NULL) {
1885 DEBUG0("Failed to get entry\n");
1889 entry->error = PCICFG_SUCCESS;
1893 entry->error = PCICFG_FAILURE;
1904 (void) pcicfg_setup_bridge(entry, handle, dip);
1909 entry->io_last;
1913 entry->memory_last;
1917 pcicfg_bridge_assign, (void *)entry);
1920 (void) pcicfg_update_bridge(entry, handle);
1928 entry->error = PCICFG_FAILURE;
1932 if (entry->io_len > 0) {
1933 range[0].size_lo = entry->io_last - entry->io_base;
1936 entry->error = PCICFG_FAILURE;
1940 if (entry->memory_len > 0) {
1942 entry->memory_last - entry->memory_base;
1945 entry->error = PCICFG_FAILURE;
1974 entry->error = PCICFG_FAILURE;
1989 (void) pcicfg_get_mem(entry,
2008 (void) pcicfg_get_mem(entry,
2023 (void) pcicfg_get_io(entry,
2038 entry->error = PCICFG_FAILURE;
2050 entry->error = PCICFG_FAILURE;
2274 * For each "assigned-addresses" property entry with a length,
2380 * This should not find an existing entry - so
2551 pcicfg_get_mem(pcicfg_phdl_t *entry,
2557 new_mem = pcicfg_alloc_hole(&entry->mem_hole, &entry->memory_last,
2564 length, ddi_get_name(entry->dip));
2568 pcicfg_get_io(pcicfg_phdl_t *entry,
2578 io_last = entry->io_last;
2579 new_io = (uint32_t)pcicfg_alloc_hole(&entry->io_hole, &io_last, length);
2581 entry->io_last = (uint32_t)io_last;
2586 length, ddi_get_name(entry->dip));
2592 pcicfg_phdl_t *entry = (pcicfg_phdl_t *)hdl;
2602 entry->error = PCICFG_SUCCESS;
2604 mem_request = &entry->mem_req;
2605 io_request = &entry->io_req;
2609 entry->error = PCICFG_FAILURE;
2620 if (entry->highest_bus < pci_config_get8(handle,
2622 entry->highest_bus =
2627 entry->error = PCICFG_FAILURE;
2638 entry->memory_len = 0;
2639 entry->io_len = 0;
2640 entry->error = PCICFG_FAILURE;
2929 * For each "assigned-addresses" property entry with a length,
3324 * Since the config space "reg" entry should have been
3801 pcicfg_setup_bridge(pcicfg_phdl_t *entry,
3809 pci_config_put8(handle, PCI_BCNF_SUBBUS, entry->highest_bus);
3851 PCICFG_HIWORD(PCICFG_LOADDR(entry->memory_last)));
3857 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(entry->io_last))));
3859 PCICFG_HIWORD(PCICFG_LOADDR(entry->io_last)));
3888 pcicfg_update_bridge(pcicfg_phdl_t *entry,
3898 PCICFG_ROUND_DOWN(entry->memory_last,
3903 PCICFG_ROUND_DOWN(entry->memory_last,
3910 if ((length = (PCICFG_ROUND_UP(entry->memory_last,
3911 PCICFG_MEMGRAN) - entry->memory_last)) > 0) {
3912 (void) pcicfg_get_mem(entry, length, NULL);
3922 PCICFG_LOADDR(PCICFG_ROUND_DOWN(entry->io_last,
3926 PCICFG_HIWORD(PCICFG_LOADDR(PCICFG_ROUND_DOWN(entry->io_last,
3935 if ((length = (PCICFG_ROUND_UP(entry->io_last,
3936 PCICFG_IOGRAN) - entry->io_last)) > 0) {
3937 (void) pcicfg_get_io(entry, length, NULL);
4738 * probed entry. The bus resource allocation