Lines Matching defs:counter
56 JBC_PIC0_EVT_MASK, /* JBC counter 0 */
57 JBC_PIC1_EVT_MASK, /* JBC counter 1 */
58 IMU_PIC0_EVT_MASK, /* IMU counter 0 */
59 IMU_PIC1_EVT_MASK, /* IMU counter 1 */
60 MMU_PIC0_EVT_MASK, /* MMU counter 0 */
61 MMU_PIC1_EVT_MASK, /* MMU counter 1 */
62 TLU_PIC0_EVT_MASK, /* TLU counter 0 */
63 TLU_PIC1_EVT_MASK, /* TLU counter 1 */
64 TLU_PIC2_EVT_MASK, /* TLU counter 2 */
65 LPU_PIC0_EVT_MASK, /* LPU counter 1 */
66 LPU_PIC1_EVT_MASK /* LPU counter 2 */
71 PIC0_EVT_SEL_SHIFT, /* JBC counter 0 */
72 PIC1_EVT_SEL_SHIFT, /* JBC counter 1 */
73 PIC0_EVT_SEL_SHIFT, /* IMU counter 0 */
74 PIC1_EVT_SEL_SHIFT, /* IMU counter 1 */
75 PIC0_EVT_SEL_SHIFT, /* MMU counter 0 */
76 PIC1_EVT_SEL_SHIFT, /* MMU counter 1 */
77 PIC0_EVT_SEL_SHIFT, /* TLU counter 0 */
78 PIC1_EVT_SEL_SHIFT, /* TLU counter 1 */
79 PIC2_EVT_SEL_SHIFT, /* TLU counter 2 */
80 PIC0_EVT_SEL_SHIFT, /* LPU counter 1 */
81 PIC2_EVT_SEL_SHIFT /* LPU counter 2 */
181 fpc_get_counter_reg_index(fire_perfcnt_t regtype, int counter)
184 "fpc_get_counter_reg_index: regtype:%d, counter:%d, bounds:%d\n",
185 regtype, counter, counters_per_type[regtype]);
186 if (BOUNDS_CHECK_FAILS(counter, counters_per_type[regtype]))
188 FPC_DBG1("returning: %d\n", first_reg_of_type[regtype] + counter);
189 return (first_reg_of_type[regtype] + counter);
194 * Program a performance counter.
196 * reggroup is which type of counter.
197 * counter is the counter number.
198 * event is the event to program for that counter.
210 int num_counters, counter;
235 for (counter = 0; counter < num_counters; counter++) {
237 counter_index = fpc_get_counter_reg_index(reggroup, counter);
243 FPC_DBG1("Zeroing counter %d\n", counter_index);
266 * Read a performance counter.
268 * reggroup is which type of counter.
269 * event_p returns the event programmed for that counter.
270 * values returns the counter values.
280 int num_counters, counter;
298 for (counter = 0; counter < num_counters; counter++) {
299 counter_index = fpc_get_counter_reg_index(reggroup, counter);
302 &values[counter], IS_READ)) != SUCCESS)
306 PRIx64 "\n", reggroup, counter, rval, values[counter]);