Lines Matching defs:phys_spec
1268 pci_alloc_resource(dev_info_t *dip, pci_regspec_t phys_spec)
1281 l = phys_spec.pci_size_low;
1294 if (assigned[i].pci_phys_hi == phys_spec.pci_phys_hi) {
1296 phys_spec.pci_size_low) {
1315 PCI_REG_BDFR_G(phys_spec.pci_phys_hi)) {
1320 PCI_REG_ADDR_G(phys_spec.pci_phys_hi)) {
1325 phys_spec.pci_phys_hi);
1332 phys_spec.pci_size_low);
1334 phys_spec.pci_size_low = l;
1348 config.pci_phys_hi = PCI_CONF_ADDR_MASK & phys_spec.pci_phys_hi;
1386 offset = PCI_REG_REG_G(phys_spec.pci_phys_hi);
1390 if (PCI_REG_REG_G(phys_spec.pci_phys_hi) == PCI_CONF_ROM) {
1409 phys_spec.pci_phys_low = LOADDR(answer);
1410 phys_spec.pci_phys_mid = HIADDR(answer);
1414 switch (PCI_REG_ADDR_G(phys_spec.pci_phys_hi)) {
1418 if (phys_spec.pci_phys_hi & PCI_REG_REL_M) {
1425 phys_spec.pci_phys_low,
1426 phys_spec.pci_phys_mid);
1455 phys_spec.pci_phys_low = LOADDR(answer);
1456 phys_spec.pci_phys_mid = HIADDR(answer);
1461 phys_spec.pci_phys_hi ^= PCI_ADDR_MEM64 ^
1469 if (phys_spec.pci_phys_hi & PCI_REG_REL_M) {
1476 phys_spec.pci_phys_low;
1502 phys_spec.pci_phys_low = LOADDR(answer);
1508 if (phys_spec.pci_phys_hi & PCI_REG_REL_M) {
1515 phys_spec.pci_phys_low;
1539 phys_spec.pci_phys_low = LOADDR(answer);
1552 if (pfc_update_assigned_prop(dip, &phys_spec)) {
1563 pci_free_resource(dev_info_t *dip, pci_regspec_t phys_spec)
1575 config.pci_phys_hi = PCI_CONF_ADDR_MASK & phys_spec.pci_phys_hi;
1608 offset = PCI_REG_REG_G(phys_spec.pci_phys_hi);
1616 l = phys_spec.pci_size_low;
1618 if (PCI_REG_REG_G(phys_spec.pci_phys_hi) == PCI_CONF_ROM) {
1620 if (ndi_ra_free(ddi_get_parent(dip), phys_spec.pci_phys_low,
1631 switch (PCI_REG_ADDR_G(phys_spec.pci_phys_hi)) {
1635 LADDR(phys_spec.pci_phys_low,
1636 phys_spec.pci_phys_mid),
1648 phys_spec.pci_phys_low,
1659 phys_spec.pci_phys_low,
1678 phys_spec.pci_phys_hi);
1680 if (pfc_remove_assigned_prop(dip, &phys_spec)) {
1692 pci_map_phys(dev_info_t *dip, pci_regspec_t *phys_spec,
1711 mr.map_obj.rp = (struct regspec *)phys_spec;