Lines Matching refs:fas

46  * fas - QLogic fas366 wide/fast SCSI Processor HBA driver with
107 static struct fas	*fas_head;	/* link all softstate structures */
108 static struct fas	*fas_tail;	/* for fas_watch()		*/
115 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", fas::f_quiesce_timeid))
141 static void fas_test_abort(struct fas *fas, int slot);
144 static void fas_test_reset(struct fas *fas, int slot);
198 static int fas_prepare_pkt(struct fas *fas, struct fas_cmd *sp);
199 static int fas_alloc_tag(struct fas *fas, struct fas_cmd *sp);
200 static int fas_accept_pkt(struct fas *fas, struct fas_cmd *sp, int flag);
201 static void fas_empty_waitQ(struct fas *fas);
202 static void fas_move_waitQ_to_readyQ(struct fas *fas);
203 static void fas_check_waitQ_and_mutex_exit(struct fas *fas);
204 static int fas_istart(struct fas *fas);
205 static int fas_ustart(struct fas *fas);
206 static int fas_startcmd(struct fas *fas, struct fas_cmd *sp);
208 static int fas_pkt_alloc_extern(struct fas *fas, struct fas_cmd *sp,
210 static void fas_pkt_destroy_extern(struct fas *fas, struct fas_cmd *sp);
214 static int fas_finish(struct fas *fas);
215 static void fas_handle_qfull(struct fas *fas, struct fas_cmd *sp);
217 static int fas_dopoll(struct fas *fas, int timeout);
218 static void fas_runpoll(struct fas *fas, short slot, struct fas_cmd *sp);
220 static int fas_intr_svc(struct	fas *fas);
221 static int fas_phasemanage(struct fas *fas);
222 static int fas_handle_unknown(struct fas *fas);
223 static int fas_handle_cmd_start(struct fas *fas);
224 static int fas_handle_cmd_done(struct fas *fas);
225 static int fas_handle_msg_out_start(struct fas *fas);
226 static int fas_handle_msg_out_done(struct fas *fas);
227 static int fas_handle_clearing(struct fas *fas);
228 static int fas_handle_data_start(struct fas *fas);
229 static int fas_handle_data_done(struct fas *fas);
230 static int fas_handle_c_cmplt(struct fas *fas);
231 static int fas_handle_msg_in_start(struct fas *fas);
232 static int fas_handle_more_msgin(struct fas *fas);
233 static int fas_handle_msg_in_done(struct fas *fas);
234 static int fas_onebyte_msg(struct fas *fas);
235 static int fas_twobyte_msg(struct fas *fas);
236 static int fas_multibyte_msg(struct fas *fas);
237 static void fas_revert_to_async(struct fas *fas, int tgt);
238 static int fas_finish_select(struct fas *fas);
239 static int fas_reselect_preempt(struct fas *fas);
240 static int fas_reconnect(struct fas *fas);
241 static int fas_handle_selection(struct fas *fas);
242 static void fas_head_of_readyQ(struct fas *fas, struct fas_cmd *sp);
243 static int fas_handle_gross_err(struct fas *fas);
244 static int fas_illegal_cmd_or_bus_reset(struct fas *fas);
245 static int fas_check_dma_error(struct fas *fas);
247 static void fas_make_sdtr(struct fas *fas, int msgout_offset, int target);
248 static void fas_make_wdtr(struct fas *fas, int msgout_offset, int target,
250 static void fas_update_props(struct fas *fas, int tgt);
251 static void fas_update_this_prop(struct fas *fas, char *property, int value);
257 static void fas_watchsubr(struct fas *fas);
258 static void fas_cmd_timeout(struct fas *fas, int slot);
259 static void fas_sync_wide_backoff(struct fas *fas, struct fas_cmd *sp,
261 static void fas_reset_sync_wide(struct fas *fas);
262 static void fas_set_wide_conf3(struct fas *fas, int target, int width);
263 static void fas_force_renegotiation(struct fas *fas, int target);
265 static int fas_set_new_window(struct fas *fas, struct fas_cmd *sp);
266 static int fas_restore_pointers(struct fas *fas, struct fas_cmd *sp);
267 static int fas_next_window(struct fas *fas, struct fas_cmd *sp, uint64_t end);
270 static void fas_log(struct fas *fas, int level, const char *fmt, ...);
272 static void fas_printf(struct fas *fas, const char *fmt, ...);
273 static void fas_printstate(struct fas *fas, char *msg);
274 static void fas_dump_cmd(struct fas *fas, struct fas_cmd *sp);
275 static void fas_short_dump_cmd(struct fas *fas, struct fas_cmd *sp);
280 static int fas_do_proxy_cmd(struct fas *fas, struct fas_cmd *sp,
283 static void fas_internal_reset(struct fas *fas, int reset_action);
284 static int fas_alloc_active_slots(struct fas *fas, int slot, int flag);
286 static int fas_abort_curcmd(struct fas *fas);
287 static int fas_abort_cmd(struct fas *fas, struct fas_cmd *sp, int slot);
290 static int fas_remove_from_readyQ(struct fas *fas, struct fas_cmd *sp,
292 static void fas_flush_readyQ(struct fas *fas, int slot);
293 static void fas_flush_tagQ(struct fas *fas, int slot);
294 static void fas_flush_cmd(struct fas *fas, struct fas_cmd *sp,
296 static int fas_abort_connected_cmd(struct fas *fas, struct fas_cmd *sp,
298 static int fas_abort_disconnected_cmd(struct fas *fas, struct scsi_address *ap,
300 static void fas_mark_packets(struct fas *fas, int slot, uchar_t reason,
302 static void fas_set_pkt_reason(struct fas *fas, struct fas_cmd *sp,
305 static int fas_reset_bus(struct fas *fas);
306 static int fas_reset_recovery(struct fas *fas);
307 static int fas_reset_connected_cmd(struct fas *fas, struct scsi_address *ap);
308 static int fas_reset_disconnected_cmd(struct fas *fas, struct scsi_address *ap);
309 static void fas_start_watch_reset_delay(struct fas *);
310 static void fas_setup_reset_delay(struct fas *fas);
312 static int fas_watch_reset_delay_subr(struct fas *fas);
313 static void fas_reset_cleanup(struct fas *fas, int slot);
319 static void fas_set_throttles(struct fas *fas, int slot,
321 static void fas_set_all_lun_throttles(struct fas *fas, int slot, int what);
322 static void fas_full_throttle(struct fas *fas, int slot);
323 static void fas_remove_cmd(struct fas *fas, struct fas_cmd *sp, int timeout);
324 static void fas_decrement_ncmds(struct fas *fas, struct fas_cmd *sp);
326 static int fas_quiesce_bus(struct fas *fas);
327 static int fas_unquiesce_bus(struct fas *fas);
329 static int fas_check_outstanding(struct fas *fas);
331 static int fas_create_arq_pkt(struct fas *fas, struct scsi_address *ap);
332 static int fas_delete_arq_pkt(struct fas *fas, struct scsi_address *ap);
333 static int fas_handle_sts_chk(struct fas *fas, struct fas_cmd *sp);
336 void fas_call_pkt_comp(struct fas *fas, struct fas_cmd *sp);
337 void fas_empty_callbackQ(struct fas *fas);
338 int fas_init_callbacks(struct fas *fas);
339 void fas_destroy_callbacks(struct fas *fas);
341 static int fas_check_dma_error(struct fas *fas);
342 static int fas_init_chip(struct fas *fas, uchar_t id);
344 static void fas_read_fifo(struct fas *fas);
345 static void fas_write_fifo(struct fas *fas, uchar_t *buf, int length, int pad);
348 static void fas_reg_cmd_write(struct fas *fas, uint8_t cmd);
349 static void fas_reg_write(struct fas *fas, volatile uint8_t *p, uint8_t what);
350 static uint8_t fas_reg_read(struct fas *fas, volatile uint8_t *p);
352 static void fas_dma_reg_write(struct fas *fas, volatile uint32_t *p,
354 static uint32_t fas_dma_reg_read(struct fas *fas, volatile uint32_t *p);
356 #define	fas_reg_cmd_write(fas, cmd) \
357 	fas->f_reg->fas_cmd = (cmd), fas->f_last_cmd = (cmd)
358 #define	fas_reg_write(fas, p, what)  *(p) = (what)
359 #define	fas_reg_read(fas, p) *(p)
360 #define	fas_dma_reg_write(fas, p, what)  *(p) = (what)
361 #define	fas_dma_reg_read(fas, p) *(p)
403 	rval = ddi_soft_state_init(&fas_state, sizeof (struct fas),
464 	struct fas *fas;
469 	fas = TRAN2FAS(tran);
475 	mutex_enter(FAS_MUTEX(fas));
476 	fas_force_renegotiation(fas, tgt);
477 	mutex_exit(FAS_MUTEX(fas));
487 	mutex_enter(FAS_MUTEX(fas));
489 	    ((fas->f_target_scsi_options_defined & (1 << tgt)) == 0)) {
494 			fas->f_target_scsi_options[tgt] = options;
495 			fas_log(fas, CE_NOTE,
497 			    fas->f_target_scsi_options[tgt]);
498 			fas_force_renegotiation(fas, tgt);
501 	mutex_exit(FAS_MUTEX(fas));
504 	    tgt, fas->f_target_scsi_options[tgt]);
524 	struct fas	*fas = NULL;
553 		fas = TRAN2FAS(tran);
554 		if (!fas) {
562 		mutex_enter(FAS_MUTEX(fas));
563 		fas_internal_reset(fas,
566 		(void) fas_reset_bus(fas);
568 		fas->f_suspended = 0;
571 		(void) fas_istart(fas);
572 		fas_check_waitQ_and_mutex_exit(fas);
596 		    "fas%d: device in slave-only slot", instance);
609 		    "fas%d: Device is using a hilevel intr", instance);
618 		    "fas%d: cannot allocate soft state", instance);
622 	fas = (struct fas *)ddi_get_soft_state(fas_state, instance);
624 	if (fas == NULL) {
637 	    &dev_attr, &fas->f_dmar_acc_handle) != DDI_SUCCESS) {
638 		cmn_err(CE_WARN, "fas%d: cannot map dma", instance);
644 	    &dev_attr, &fas->f_regs_acc_handle) != DDI_SUCCESS) {
646 		    "fas%d: unable to map fas366 registers", instance);
652 	    DDI_DMA_SLEEP, NULL, &fas->f_dmahandle) != DDI_SUCCESS) {
654 		    "fas%d: cannot alloc dma handle", instance);
661 	if (ddi_dma_mem_alloc(fas->f_dmahandle,
664 	    NULL, (caddr_t *)&fas->f_cmdarea, &rlen,
665 	    &fas->f_cmdarea_acc_handle) != DDI_SUCCESS) {
667 		    "fas%d: cannot alloc cmd area", instance);
671 	fas->f_reg = fasreg;
672 	fas->f_dma = dmar;
673 	fas->f_instance  = instance;
675 	if (ddi_dma_addr_bind_handle(fas->f_dmahandle,
676 	    NULL, (caddr_t)fas->f_cmdarea,
678 	    &fas->f_dmacookie, &count) != DDI_DMA_MAPPED) {
680 		    "fas%d: cannot bind cmdarea", instance);
698 	fas->f_tran			= tran;
699 	fas->f_dev			= dip;
700 	tran->tran_hba_private		= fas;
725 	fas->f_force_async = 0;
732 	fas->f_nowide = fas->f_notag = ALL_TARGETS;
733 	fas->f_force_narrow = ALL_TARGETS;
743 	fas->f_dslot = NLUNS_PER_TARGET;
754 		(void) fas_alloc_active_slots(fas, slot, KM_SLEEP);
761 		fas->f_qfull_retries[i] = QFULL_RETRIES;
762 		fas->f_qfull_retry_interval[i] =
770 	fas_set_throttles(fas, 0, N_SLOTS, MAX_THROTTLE);
775 	fas->f_props_update = 0;
780 	fas->f_fasconf = DEFAULT_HOSTID;
787 		fas_log(fas, CE_NOTE, "?initiator SCSI ID now %d\n", id);
788 		fas->f_fasconf = (uchar_t)id;
794 	fas->f_dma_attr = fas_dma_attr;
795 	fas->f_dma_attr->dma_attr_burstsizes &=
796 	    ddi_dma_burstsizes(fas->f_dmahandle);
799 	fas->f_dma_attr->dma_attr_burstsizes &= fas_burstsizes_limit;
800 	IPRINTF1("dma burstsize=%x\n", fas->f_dma_attr->dma_attr_burstsizes);
805 	if (scsi_hba_attach_setup(dip, fas->f_dma_attr, tran, 0) !=
807 		fas_log(fas, CE_WARN, "scsi_hba_attach_setup failed");
815 	fas->f_scsi_options = ddi_prop_get_int(DDI_DEV_T_ANY,
832 			fas->f_hm_rev = 0x20;
833 			fas_log(fas, CE_WARN,
837 			fas->f_hm_rev = 0x10;
838 			fas_log(fas, CE_WARN,
843 		fas->f_hm_rev = 0x21;
844 		fas_log(fas, CE_WARN, "obsolete rev 2.1 FEPS chip");
846 		fas->f_hm_rev = (uchar_t)hm_rev;
847 		fas_log(fas, CE_NOTE, "?rev %x.%x FEPS chip\n",
851 	if ((fas->f_scsi_options & SCSI_OPTIONS_SYNC) == 0) {
852 		fas->f_nosync = ALL_TARGETS;
855 	if ((fas->f_scsi_options & SCSI_OPTIONS_WIDE) == 0) {
856 		fas->f_nowide = ALL_TARGETS;
865 		fas->f_target_scsi_options[i] = ddi_prop_get_int(
868 		if (fas->f_target_scsi_options[i] != -1) {
869 			fas_log(fas, CE_NOTE, "?target%x-scsi-options=0x%x\n",
870 			    i, fas->f_target_scsi_options[i]);
871 			fas->f_target_scsi_options_defined |= 1 << i;
873 			fas->f_target_scsi_options[i] = fas->f_scsi_options;
875 		if (((fas->f_target_scsi_options[i] &
877 		    (fas->f_target_scsi_options[i] & SCSI_OPTIONS_TAG)) {
878 			fas->f_target_scsi_options[i] &= ~SCSI_OPTIONS_TAG;
879 			fas_log(fas, CE_WARN,
884 	fas->f_scsi_tag_age_limit =
888 	fas->f_scsi_reset_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
890 	if (fas->f_scsi_reset_delay == 0) {
891 		fas_log(fas, CE_NOTE,
894 		fas->f_scsi_reset_delay = SCSI_DEFAULT_RESET_DELAY;
900 	if (ddi_get_iblock_cookie(dip, (uint_t)0, &fas->f_iblock)
906 	mutex_init(&fas->f_mutex, NULL, MUTEX_DRIVER, fas->f_iblock);
907 	cv_init(&fas->f_cv, NULL, CV_DRIVER, NULL);
912 	mutex_init(&fas->f_waitQ_mutex, NULL, MUTEX_DRIVER, fas->f_iblock);
919 	if (fas_init_callbacks(fas)) {
928 	(void) sprintf(buf, "fas%d", instance);
929 	fas->f_intr_kstat = kstat_create("fas", instance, buf, "controller", \
931 	if (fas->f_intr_kstat)
932 		kstat_install(fas->f_intr_kstat);
937 	mutex_enter(FAS_MUTEX(fas));
938 	if (ddi_add_intr(dip, (uint_t)0, &fas->f_iblock, NULL,
939 	    fas_intr, (caddr_t)fas)) {
940 		cmn_err(CE_WARN, "fas: cannot add intr");
941 		mutex_exit(FAS_MUTEX(fas));
947 	 * initialize fas chip
949 	if (fas_init_chip(fas, id))	{
950 		cmn_err(CE_WARN, "fas: cannot initialize");
951 		mutex_exit(FAS_MUTEX(fas));
954 	mutex_exit(FAS_MUTEX(fas));
959 	(void) sprintf(buf, "fas%d_cache", instance);
960 	fas->f_kmem_cache = kmem_cache_create(buf,
963 	    NULL, (void *)fas, NULL, 0);
964 	if (fas->f_kmem_cache == NULL) {
965 		cmn_err(CE_WARN, "fas: cannot create kmem_cache");
973 	 * add this fas to the list, this makes debugging easier
974 	 * and fas_watch() needs it to walk thru all fas's
978 		fas_head = fas;
980 		fas_tail->f_next = fas;
982 	fas_tail = fas; 	/* point to last fas in list */
994 			fas_log(fas, CE_NOTE, "?scsi-watchdog-tick=%d\n",
999 		IPRINTF2("fas scsi watchdog tick=%x, fas_tick=%lx\n",
1013 	cmn_err(CE_WARN, "fas%d: cannot attach", instance);
1014 	if (fas) {
1016 			struct f_slots *active = fas->f_active[slot];
1019 				fas->f_active[slot] = NULL;
1023 			mutex_destroy(&fas->f_mutex);
1024 			mutex_destroy(&fas->f_waitQ_mutex);
1025 			cv_destroy(&fas->f_cv);
1028 			ddi_remove_intr(dip, (uint_t)0, fas->f_iblock);
1033 		if (fas->f_intr_kstat) {
1034 			kstat_delete(fas->f_intr_kstat);
1042 		if (fas->f_kmem_cache) {
1043 			kmem_cache_destroy(fas->f_kmem_cache);
1045 		if (fas->f_cmdarea) {
1047 				(void) ddi_dma_unbind_handle(fas->f_dmahandle);
1049 			ddi_dma_mem_free(&fas->f_cmdarea_acc_handle);
1051 		if (fas->f_dmahandle) {
1052 			ddi_dma_free_handle(&fas->f_dmahandle);
1054 		fas_destroy_callbacks(fas);
1055 		if (fas->f_regs_acc_handle) {
1056 			ddi_regs_map_free(&fas->f_regs_acc_handle);
1058 		if (fas->f_dmar_acc_handle) {
1059 			ddi_regs_map_free(&fas->f_dmar_acc_handle);
1072 	struct fas	*fas, *nfas;
1086 		fas = TRAN2FAS(tran);
1087 		if (!fas) {
1091 		mutex_enter(FAS_MUTEX(fas));
1093 		fas->f_suspended = 1;
1095 		if (fas->f_ncmds) {
1096 			(void) fas_reset_bus(fas);
1097 			(void) fas_dopoll(fas, SHORT_POLL_TIMEOUT);
1100 		 * disable dma and fas interrupt
1102 		fas->f_dma_csr &= ~DMA_INTEN;
1103 		fas->f_dma_csr &= ~DMA_ENDVMA;
1104 		fas_dma_reg_write(fas, &fas->f_dma->dma_csr, fas->f_dma_csr);
1106 		mutex_exit(FAS_MUTEX(fas));
1108 		if (fas->f_quiesce_timeid) {
1109 			(void) untimeout(fas->f_quiesce_timeid);
1110 				fas->f_quiesce_timeid = 0;
1113 		if (fas->f_restart_cmd_timeid) {
1114 			(void) untimeout(fas->f_restart_cmd_timeid);
1115 				fas->f_restart_cmd_timeid = 0;
1118 		/* Last fas? */
1161 	struct fas 	*fas, *f;
1169 	fas = TRAN2FAS(tran);
1170 	if (!fas) {
1177 	fas->f_dma_csr &= ~DMA_INTEN;
1178 	fas->f_dma->dma_csr = fas->f_dma_csr;
1179 	ddi_remove_intr(dip, (uint_t)0, fas->f_iblock);
1186 	if (fas_head == fas) {
1187 		f = fas_head = fas->f_next;
1189 		for (f = fas_head; f != (struct fas *)NULL; f = f->f_next) {
1190 			if (f->f_next == fas) {
1191 				f->f_next = fas->f_next;
1202 		if (f == (struct fas *)NULL) {
1203 			cmn_err(CE_WARN, "fas_dr_detach: fas instance not"
1212 	if (fas_tail == fas)
1217 	if (fas->f_intr_kstat)
1218 		kstat_delete(fas->f_intr_kstat);
1220 	fas_destroy_callbacks(fas);
1222 	scsi_hba_reset_notify_tear_down(fas->f_reset_notify_listf);
1229 		struct f_slots *active = fas->f_active[slot];
1245 			fas->f_active[slot] = NULL;
1247 		ASSERT(fas->f_tcmds[slot] == 0);
1253 	fas->f_flags |= FAS_FLG_NOTIMEOUTS;
1256 	if (fas->f_quiesce_timeid) {
1257 		(void) untimeout(fas->f_quiesce_timeid);
1261 	 * last fas? ... if active, CANCEL watch threads.
1264 	if (fas_head == (struct fas *)NULL) {
1283 	if (fas->f_restart_cmd_timeid) {
1284 		(void) untimeout(fas->f_restart_cmd_timeid);
1285 		fas->f_restart_cmd_timeid = 0;
1294 			if (fas->f_arq_pkt[slot]) {
1299 				(void) fas_delete_arq_pkt(fas, &sa);
1307 	mutex_destroy(&fas->f_waitQ_mutex);
1308 	mutex_destroy(&fas->f_mutex);
1309 	cv_destroy(&fas->f_cv);
1315 	if (fas->f_kmem_cache) {
1316 		kmem_cache_destroy(fas->f_kmem_cache);
1319 	if (fas->f_cmdarea != (uchar_t *)NULL) {
1320 		(void) ddi_dma_unbind_handle(fas->f_dmahandle);
1321 		ddi_dma_mem_free(&fas->f_cmdarea_acc_handle);
1324 	if (fas->f_dmahandle != (ddi_dma_handle_t)NULL) {
1325 		ddi_dma_free_handle(&fas->f_dmahandle);
1328 	if (fas->f_regs_acc_handle) {
1329 		ddi_regs_map_free(&fas->f_regs_acc_handle);
1331 	if (fas->f_dmar_acc_handle) {
1332 		ddi_regs_map_free(&fas->f_dmar_acc_handle);
1358 fas_quiesce_bus(struct fas *fas)
1360 	mutex_enter(FAS_MUTEX(fas));
1363 	    fas->f_ncmds, fas->f_ndisc, fas->f_softstate);
1364 	fas_set_throttles(fas, 0, N_SLOTS, HOLD_THROTTLE);
1365 	if (fas_check_outstanding(fas)) {
1366 		fas->f_softstate |= FAS_SS_DRAINING;
1367 		fas->f_quiesce_timeid = timeout(fas_ncmds_checkdrain,
1368 		    fas, (FAS_QUIESCE_TIMEOUT * drv_usectohz(1000000)));
1369 		if (cv_wait_sig(FAS_CV(fas), FAS_MUTEX(fas)) == 0) {
1374 			fas->f_softstate &= ~FAS_SS_DRAINING;
1375 			fas_set_throttles(fas, 0, N_SLOTS, MAX_THROTTLE);
1376 			(void) fas_istart(fas);
1377 			if (fas->f_quiesce_timeid != 0) {
1378 				mutex_exit(FAS_MUTEX(fas));
1380 				(void) untimeout(fas->f_quiesce_timeid);
1381 				fas->f_quiesce_timeid = 0;
1385 			mutex_exit(FAS_MUTEX(fas));
1389 			ASSERT(fas->f_quiesce_timeid == 0);
1390 			fas->f_softstate &= ~FAS_SS_DRAINING;
1391 			fas->f_softstate |= FAS_SS_QUIESCED;
1392 			mutex_exit(FAS_MUTEX(fas));
1397 	mutex_exit(FAS_MUTEX(fas));
1402 fas_unquiesce_bus(struct fas *fas)
1404 	mutex_enter(FAS_MUTEX(fas));
1405 	fas->f_softstate &= ~FAS_SS_QUIESCED;
1406 	fas_set_throttles(fas, 0, N_SLOTS, MAX_THROTTLE);
1407 	(void) fas_istart(fas);
1409 	mutex_exit(FAS_MUTEX(fas));
1420 	struct fas *fas = arg;
1422 	mutex_enter(FAS_MUTEX(fas));
1424 	    fas->f_ncmds, fas->f_ndisc, fas->f_softstate);
1425 	if (fas->f_softstate & FAS_SS_DRAINING) {
1426 		fas->f_quiesce_timeid = 0;
1427 		if (fas_check_outstanding(fas) == 0) {
1429 			cv_signal(FAS_CV(fas));
1436 			fas_set_throttles(fas, 0, N_SLOTS, HOLD_THROTTLE);
1438 			fas->f_quiesce_timeid = timeout(fas_ncmds_checkdrain,
1439 			    fas, (FAS_QUIESCE_TIMEOUT * drv_usectohz(1000000)));
1442 	mutex_exit(FAS_MUTEX(fas));
1446 fas_check_outstanding(struct fas *fas)
1449 	uint_t d = ((fas->f_dslot == 0)? 1 : fas->f_dslot);
1452 	ASSERT(mutex_owned(FAS_MUTEX(fas)));
1455 		ncmds += fas->f_tcmds[slot];
1463  * fas register read/write functions with tracing
1466 fas_reg_tracing(struct fas *fas, int type, int regno, uint32_t what)
1468 	fas->f_reg_trace[fas->f_reg_trace_index++] = type;
1469 	fas->f_reg_trace[fas->f_reg_trace_index++] = regno;
1470 	fas->f_reg_trace[fas->f_reg_trace_index++] = what;
1471 	fas->f_reg_trace[fas->f_reg_trace_index++] = gethrtime();
1472 	fas->f_reg_trace[fas->f_reg_trace_index] = 0xff;
1473 	if (fas->f_reg_trace_index >= REG_TRACE_BUF_SIZE) {
1474 		fas->f_reg_trace_index = 0;
1479 fas_reg_cmd_write(struct fas *fas, uint8_t cmd)
1481 	volatile struct fasreg *fasreg = fas->f_reg;
1485 	fas->f_last_cmd = cmd;
1488 	fas_reg_tracing(fas, 0, regno, cmd);
1490 	fas->f_reg_cmds++;
1494 fas_reg_write(struct fas *fas, volatile uint8_t *p, uint8_t what)
1496 	int regno = (uintptr_t)p - (uintptr_t)fas->f_reg;
1501 	fas_reg_tracing(fas, 1, regno, what);
1503 	fas->f_reg_writes++;
1507 fas_reg_read(struct fas *fas, volatile uint8_t *p)
1510 	int regno = (uintptr_t)p - (uintptr_t)fas->f_reg;
1515 	fas_reg_tracing(fas, 2, regno, what);
1517 	fas->f_reg_reads++;
1526 fas_dma_reg_write(struct fas *fas, volatile uint32_t *p, uint32_t what)
1529 	fas->f_reg_dma_writes++;
1533 	int regno = (uintptr_t)p - (uintptr_t)fas->f_dma;
1535 	fas_reg_tracing(fas, 3, regno, what);
1541 fas_dma_reg_read(struct fas *fas, volatile uint32_t *p)
1544 	fas->f_reg_dma_reads++;
1548 	int regno = (uintptr_t)p - (uintptr_t)fas->f_dma;
1550 	fas_reg_tracing(fas, 4, regno, what);
1557 #define	FIFO_EMPTY(fas)  (fas_reg_read(fas, &fas->f_reg->fas_stat2) & \
1559 #define	FIFO_CNT(fas) \
1560 	(fas_reg_read(fas, &fas->f_reg->fas_fifo_flag) & FIFO_CNT_MASK)
1564 fas_assert_atn(struct fas *fas)
1566 	fas_reg_cmd_write(fas, CMD_SET_ATN);
1573 #define	fas_assert_atn(fas)  fas_reg_cmd_write(fas, CMD_SET_ATN)
1580 #define	FAS_DMA_WRITE(fas, count, base, cmd) { \
1581 	volatile struct fasreg *fasreg = fas->f_reg; \
1582 	volatile struct dma *dmar = fas->f_dma; \
1583 	ASSERT((fas_dma_reg_read(fas, &dmar->dma_csr) & DMA_ENDVMA) == 0); \
1585 	fas_reg_cmd_write(fas, cmd); \
1586 	fas_dma_reg_write(fas, &dmar->dma_count, count); \
1587 	fas->f_dma_csr |= \
1589 	fas_dma_reg_write(fas, &dmar->dma_addr, (fas->f_lastdma = base)); \
1590 	fas_dma_reg_write(fas, &dmar->dma_csr, fas->f_dma_csr); \
1593 #define	FAS_DMA_WRITE_SETUP(fas, count, base) { \
1594 	volatile struct fasreg *fasreg = fas->f_reg; \
1595 	volatile struct dma *dmar = fas->f_dma; \
1596 	ASSERT((fas_dma_reg_read(fas, &dmar->dma_csr) & DMA_ENDVMA) == 0); \
1598 	fas_dma_reg_write(fas, &dmar->dma_count, count); \
1599 	fas->f_dma_csr |= \
1601 	fas_dma_reg_write(fas, &dmar->dma_addr, (fas->f_lastdma = base)); \
1605 #define	FAS_DMA_READ(fas, count, base, dmacount, cmd) { \
1606 	volatile struct fasreg *fasreg = fas->f_reg; \
1607 	volatile struct dma *dmar = fas->f_dma; \
1608 	ASSERT((fas_dma_reg_read(fas, &dmar->dma_csr) & DMA_ENDVMA) == 0); \
1610 	fas_reg_cmd_write(fas, cmd); \
1611 	fas->f_dma_csr |= \
1612 	    (fas->f_dma_csr &	~DMA_WRITE) | DMA_ENDVMA | DMA_DSBL_DRAIN; \
1613 	fas_dma_reg_write(fas, &dmar->dma_count, dmacount); \
1614 	fas_dma_reg_write(fas, &dmar->dma_addr, (fas->f_lastdma = base)); \
1615 	fas_dma_reg_write(fas, &dmar->dma_csr, fas->f_dma_csr); \
1619 FAS_FLUSH_DMA(struct fas *fas)
1621 	fas_dma_reg_write(fas, &fas->f_dma->dma_csr, DMA_RESET);
1622 	fas->f_dma_csr |= (DMA_INTEN|DMA_TWO_CYCLE|DMA_DSBL_PARITY|
1624 	fas->f_dma_csr &= ~(DMA_ENDVMA | DMA_WRITE);
1625 	fas_dma_reg_write(fas, &fas->f_dma->dma_csr, 0);
1626 	fas_dma_reg_write(fas, &fas->f_dma->dma_csr, fas->f_dma_csr);
1627 	fas_dma_reg_write(fas, &fas->f_dma->dma_addr, 0);
1634 FAS_FLUSH_DMA_HARD(struct fas *fas)
1636 	fas_dma_reg_write(fas, &fas->f_dma->dma_csr, DMA_RESET);
1637 	fas->f_dma_csr |= (DMA_INTEN|DMA_TWO_CYCLE|DMA_DSBL_PARITY|
1639 	fas->f_dma_csr &= ~(DMA_ENDVMA | DMA_WRITE);
1640 	while (fas_dma_reg_read(fas, &fas->f_dma->dma_csr) & DMA_REQPEND)
1642 	fas_dma_reg_write(fas, &fas->f_dma->dma_csr, 0);
1643 	fas_dma_reg_write(fas, &fas->f_dma->dma_csr, fas->f_dma_csr);
1644 	fas_dma_reg_write(fas, &fas->f_dma->dma_addr, 0);
1650 #define	FAS_SET_PERIOD_OFFSET_CONF3_REGS(fas, target) \
1653 	period = fas->f_sync_period[target] & SYNC_PERIOD_MASK; \
1654 	offset = fas->f_offset[target]; \
1655 	conf3  = fas->f_fasconf3[target]; \
1656 	if ((period != fas->f_period_reg_last) || \
1657 	    (offset != fas->f_offset_reg_last) || \
1658 	    (conf3 != fas->f_fasconf3_reg_last)) { \
1659 		fas->f_period_reg_last = period; \
1660 		fas->f_offset_reg_last = offset; \
1661 		fas->f_fasconf3_reg_last = conf3; \
1662 		fas_reg_write(fas, &fasreg->fas_sync_period, period); \
1663 		fas_reg_write(fas, &fasreg->fas_sync_offset, offset); \
1664 		fas_reg_write(fas, &fasreg->fas_conf3, conf3); \
1674 fas_read_fifo(struct fas *fas)
1676 	int stat = fas->f_stat;
1677 	volatile struct fasreg	 *fasreg = fas->f_reg;
1680 	i = fas_reg_read(fas, &fasreg->fas_fifo_flag) & FIFO_CNT_MASK;
1684 	fas->f_fifolen = 0;
1686 		fas->f_fifo[fas->f_fifolen++] = fas_reg_read(fas,
1688 		fas->f_fifo[fas->f_fifolen++] = fas_reg_read(fas,
1691 	if (fas->f_stat2 & FAS_STAT2_ISHUTTLE)	{
1694 		fas_reg_write(fas, &fasreg->fas_fifo_data, 0);
1695 		fas->f_fifo[fas->f_fifolen++] = fas_reg_read(fas,
1698 		fas_reg_cmd_write(fas, CMD_FLUSH);
1701 	    fas->f_fifolen, stat);
1705 fas_write_fifo(struct fas *fas, uchar_t *buf, int length, int pad)
1708 	volatile struct fasreg	 *fasreg = fas->f_reg;
1712 	fas_reg_cmd_write(fas, CMD_FLUSH);
1714 		fas_reg_write(fas, &fasreg->fas_fifo_data, buf[i]);
1716 			fas_reg_write(fas, &fasreg->fas_fifo_data, 0);
1725 fas_init_chip(struct fas *fas, uchar_t initiator_id)
1737 	    fas->f_dev, DDI_PROP_DONTPASS, prop_cfreq, -1);
1740 		fas_log(fas, CE_WARN, "Bad clock frequency");
1744 	fas->f_clock_conv = clock_conv;
1745 	fas->f_clock_cycle = CLOCK_PERIOD(i);
1746 	ticks = FAS_CLOCK_TICK(fas);
1747 	fas->f_stval = FAS_CLOCK_TIMEOUT(ticks, fas_selection_timeout);
1750 	    i, fas->f_clock_conv, fas->f_clock_cycle,
1751 	    ticks, fas->f_stval);
1755 	fas->f_fasconf |= FAS_CONF_PAREN;
1756 	fas->f_fasconf2 = (uchar_t)(FAS_CONF2_FENABLE | FAS_CONF2_XL32);
1766 		fas->f_fasconf3[i] = initial_conf3;
1771 	 * delay per fas in boot and also causes busy conditions in some
1774 	fas_internal_reset(fas, FAS_RESET_SOFTC|FAS_RESET_FAS|FAS_RESET_DMA);
1780 		if (fas->f_target_scsi_options[i] & SCSI_OPTIONS_SYNC) {
1781 			fas->f_offset[i] = fas_default_offset |
1782 			    fas->f_req_ack_delay;
1784 			fas->f_offset[i] = 0;
1786 		if (fas->f_target_scsi_options[i] & SCSI_OPTIONS_FAST) {
1787 			fas->f_neg_period[i] =
1788 			    (uchar_t)MIN_SYNC_PERIOD(fas);
1790 			fas->f_neg_period[i] =
1801 fas_internal_reset(struct fas *fas, int reset_action)
1803 	volatile struct fasreg *fasreg = fas->f_reg;
1804 	volatile struct dma *dmar = fas->f_dma;
1807 		fas_reg_cmd_write(fas, CMD_RESET_SCSI);
1808 		fas_setup_reset_delay(fas);
1811 	FAS_FLUSH_DMA_HARD(fas); /* resets and reinits the dma */
1819 		int burstsizes = fas->f_dma_attr->dma_attr_burstsizes;
1822 			fas->f_dma_csr |= DMA_BURST64;
1825 			fas->f_dma_csr |= DMA_BURST32;
1829 		if ((fas->f_hm_rev > 0x20) && (fas_enable_sbus64) &&
1830 		    (ddi_dma_set_sbus64(fas->f_dmahandle, burstsizes) ==
1833 			fas->f_dma_csr |= DMA_WIDE_EN;
1845 		fas_reg_cmd_write(fas, CMD_RESET_FAS);
1846 		fas_reg_cmd_write(fas, CMD_NOP | CMD_DMA);
1847 		fas_reg_cmd_write(fas, CMD_NOP | CMD_DMA);
1853 		fas_reg_write(fas, &fasreg->fas_clock_conv,
1854 		    (fas->f_clock_conv & CLOCK_MASK));
1856 		fas_reg_write(fas, &fasreg->fas_timeout, fas->f_stval);
1861 		fas->f_idcode = idcode =
1862 		    fas_reg_read(fas, &fasreg->fas_id_code);
1864 		fas->f_type = FAS366;
1867 		dmarev = fas_dma_reg_read(fas, &dmar->dma_csr);
1871 		fas_reg_write(fas, &fasreg->fas_conf, fas->f_fasconf);
1872 		fas_reg_write(fas, &fasreg->fas_conf2, fas->f_fasconf2);
1874 		fas->f_req_ack_delay = DEFAULT_REQ_ACK_DELAY;
1879 		(void) fas_reg_read(fas, &fasreg->fas_intr);
1883 		fas->f_wdtr_sent = fas->f_sdtr_sent = 0;
1884 		fas->f_wide_known = fas->f_sync_known = 0;
1885 		fas->f_wide_enabled = fas->f_sync_enabled = 0;
1886 		fas->f_omsglen = 0;
1887 		fas->f_cur_msgout[0] = fas->f_last_msgout =
1888 		    fas->f_last_msgin = INVALID_MSG;
1889 		fas->f_abort_msg_sent = fas->f_reset_msg_sent = 0;
1890 		fas->f_next_slot = 0;
1891 		fas->f_current_sp = NULL;
1892 		fas->f_fifolen = 0;
1893 		fas->f_fasconf3_reg_last = fas->f_offset_reg_last =
1894 		    fas->f_period_reg_last = 0xff;
1896 		New_state(fas, STATE_FREE);
1907 fas_check_ncmds(struct fas *fas)
1914 		if (fas->f_active[slot]) {
1915 			struct fas_cmd *sp = fas->f_readyf[slot];
1916 			t = fas->f_active[slot]->f_n_slots;
1922 				if (fas->f_active[slot]->f_slot[tag] != 0) {
1927 			ASSERT(n == fas->f_tcmds[slot]);
1929 		slot = NEXTSLOT(slot, fas->f_dslot);
1932 	if (total != fas->f_ncmds) {
1934 		    total, fas->f_ncmds);
1936 	ASSERT(fas->f_ncmds >= fas->f_ndisc);
1939 #define	fas_check_ncmds(fas)
1953 	struct fas *fas = ADDR2FAS(ap);
1958 	mutex_enter(FAS_MUTEX(fas));
1960 	fas_check_waitQ_and_mutex_exit(fas);
1971 	struct fas *fas = ADDR2FAS(ap);
1977 	mutex_enter(FAS_MUTEX(fas));
1979 	fas_check_waitQ_and_mutex_exit(fas);
1990 	struct fas	*fas = ADDR2FAS(ap);
1993 	    &fas->f_mutex, &fas->f_reset_notify_listf));
2003 	struct fas *fas = ADDR2FAS(ap);
2013 	struct fas *fas = ADDR2FAS(ap);
2070 	struct fas *fas = ADDR2FAS(ap);
2090 		cmd = kmem_cache_alloc(fas->f_kmem_cache, kf);
2126 				failure = fas_pkt_alloc_extern(fas, cmd,
2225 	struct fas *fas = ADDR2FAS(ap);
2251 		kmem_cache_free(fas->f_kmem_cache, (void *)sp);
2253 		fas_pkt_destroy_extern(fas, sp);
2267 fas_pkt_alloc_extern(struct fas *fas, struct fas_cmd *sp,
2299 		fas_pkt_destroy_extern(fas, sp);
2308 fas_pkt_destroy_extern(struct fas *fas, struct fas_cmd *sp)
2328 	kmem_cache_free(fas->f_kmem_cache, (void *)sp);
2340 	struct fas *fas = cdrarg;
2349 	if ((ddi_dma_alloc_handle(fas->f_dev, fas->f_dma_attr, callback,
2373 	struct fas *fas = ADDR2FAS(ap);
2397 	rval = fas_prepare_pkt(fas, sp);
2405 	 * fas mutex can be held for a long time; therefore, if the mutex is
2407 	 * the waitQ on every mutex_exit(FAS_MUTEX(fas)) but we really only
2422 		 * so we don't want to take the fas mutex but queue up
2428 		mutex_enter(&fas->f_waitQ_mutex);
2430 		if ((fas->f_state != STATE_FREE) ||
2431 		    fas->f_waitf || (intr = INTPENDING(fas))) {
2437 		 * the packet. if we fail to get the fas mutex, go back to
2441 		 * emptied the waitQ but not released the fas mutex yet
2446 		 * if another thread has the fas mutex then either this
2450 		if (mutex_tryenter(FAS_MUTEX(fas))) {
2451 			mutex_exit(&fas->f_waitQ_mutex);
2452 			rval = fas_accept_pkt(fas, sp, TRAN_BUSY_OK);
2455 			 * we didn't get the fas mutex so
2465 		mutex_enter(FAS_MUTEX(fas));
2466 		rval = fas_accept_pkt(fas, sp, TRAN_BUSY_OK);
2475 	if (fas->f_state == STATE_FREE) {
2476 		FAS_CHECK_WAITQ_AND_FAS_MUTEX_EXIT(fas);
2478 		mutex_exit(FAS_MUTEX(fas));
2483 	    "fas_scsi_start_end: fas 0x%p", fas);
2487 	if (fas->f_waitf == NULL) {
2488 		fas->f_waitb = fas->f_waitf = sp;
2491 		struct fas_cmd *dp = fas->f_waitb;
2492 		dp->cmd_forw = fas->f_waitb = sp;
2497 	 * check again the fas mutex
2501 	if ((intr == 0) && (fas->f_state == STATE_FREE) &&
2502 	    mutex_tryenter(FAS_MUTEX(fas))) {
2507 		if (fas->f_state == STATE_FREE) {
2508 			fas_empty_waitQ(fas);
2510 		mutex_exit(FAS_MUTEX(fas));
2512 	mutex_exit(&fas->f_waitQ_mutex);
2515 	    "fas_scsi_start_end: fas 0x%p", fas);
2525 fas_prepare_pkt(struct fas *fas, struct fas_cmd *sp)
2556 			if (fas_set_new_window(fas, sp)) {
2593 			fas_log(fas, CE_NOTE,
2596 			    Tgt(sp), fas->f_tcmds[slot], (void *)sp,
2597 			    fas->f_throttle[slot]);
2626 	if ((fas->f_target_scsi_options[Tgt(sp)] & SCSI_OPTIONS_DR) == 0) {
2658 fas_empty_waitQ(struct fas *fas)
2664 	ASSERT(mutex_owned(&fas->f_waitQ_mutex));
2668 	while (fas->f_waitf) {
2671 		waitf = fas->f_waitf;
2672 		waitb = fas->f_waitb;
2673 		fas->f_waitf = fas->f_waitb = NULL;
2674 		mutex_exit(&fas->f_waitQ_mutex);
2683 			rval = fas_accept_pkt(fas, sp, NO_TRAN_BUSY);
2691 				fas_set_pkt_reason(fas, sp, CMD_TRAN_ERR, 0);
2694 					fas_call_pkt_comp(fas, sp);
2698 			if (INTPENDING(fas)) {
2703 				mutex_enter(&fas->f_waitQ_mutex);
2706 					waitb->cmd_forw = fas->f_waitf;
2707 					fas->f_waitf = waitf;
2708 					if (fas->f_waitb == NULL) {
2709 						fas->f_waitb = waitb;
2716 		mutex_enter(&fas->f_waitQ_mutex);
2723 fas_move_waitQ_to_readyQ(struct fas *fas)
2729 	ASSERT(mutex_owned(FAS_MUTEX(fas)));
2730 	mutex_enter(&fas->f_waitQ_mutex);
2731 	fas_empty_waitQ(fas);
2732 	mutex_exit(&fas->f_waitQ_mutex);
2741 fas_check_waitQ_and_mutex_exit(struct fas *fas)
2743 	_NOTE(LOCK_RELEASED_AS_SIDE_EFFECT(fas->f_mutex))
2744 	FAS_CHECK_WAITQ_AND_FAS_MUTEX_EXIT(fas);
2745 	FAS_EMPTY_CALLBACKQ(fas);
2755 fas_accept_pkt(struct fas *fas, struct fas_cmd *sp, int flag)
2761 	ASSERT(mutex_owned(FAS_MUTEX(fas)));
2762 	ASSERT(fas->f_ncmds >= 0 && fas->f_ndisc >= 0);
2763 	ASSERT(fas->f_ncmds >= fas->f_ndisc);
2764 	ASSERT(fas->f_tcmds[slot] >= 0);
2771 		rval = fas_prepare_pkt(fas, sp);
2781 		fas->f_dslot = 1;
2783 		if ((fas->f_active[slot] == NULL) ||
2784 		    ((fas->f_active[slot]->f_n_slots != NTAGS) &&
2786 			(void) fas_alloc_active_slots(fas, slot, KM_NOSLEEP);
2788 		if ((fas->f_active[slot] == NULL) ||
2799 	fas_check_ncmds(fas);
2800 	fas->f_ncmds++;
2808 		fas_runpoll(fas, slot, sp);
2816 	if ((fas->f_tcmds[slot] == 0) &&
2817 	    (fas->f_throttle[slot] == DRAIN_THROTTLE)) {
2819 		ASSERT(fas->f_reset_delay[Tgt(sp)] == 0);
2820 		fas_full_throttle(fas, slot);
2829 	fas->f_total_cmds++;
2832 	if ((fas->f_readyf[slot] == NULL) && (fas->f_state == STATE_FREE) &&
2833 	    (fas->f_throttle[slot] > fas->f_tcmds[slot])) {
2834 		ASSERT(fas->f_current_sp == 0);
2835 		(void) fas_startcmd(fas, sp);
2845 			struct fas_cmd *ssp = fas->f_readyf[slot];
2849 				fas_head_of_readyQ(fas, sp);
2854 				if (fas->f_readyb[slot] == ssp) {
2855 					fas->f_readyb[slot] = sp;
2858 				fas->f_readyf[slot] = fas->f_readyb[slot] = sp;
2868 		    (fas->f_tcmds[slot] >= fas->f_throttle[slot]) &&
2869 		    (fas->f_throttle[slot] > HOLD_THROTTLE) &&
2873 			    slot, fas->f_ncmds);
2875 			fas->f_ncmds--;
2882 		} else if (fas->f_readyf[slot]) {
2883 			struct fas_cmd *dp = fas->f_readyb[slot];
2885 			fas->f_readyb[slot] = sp;
2889 			fas->f_readyf[slot] = fas->f_readyb[slot] = sp;
2900 	if (fas->f_state == STATE_FREE) {
2901 		(void) fas_istart(fas);
2905 	fas_check_ncmds(fas);
2906 	ASSERT(mutex_owned(FAS_MUTEX(fas)));
2918 fas_alloc_tag(struct fas *fas, struct fas_cmd *sp)
2925 	ASSERT(mutex_owned(FAS_MUTEX(fas)));
2927 	tag_slots = fas->f_active[slot];
2931 	tag = (fas->f_active[slot]->f_tags)++;
2932 	if (fas->f_active[slot]->f_tags >= NTAGS) {
2936 		fas->f_active[slot]->f_tags = 1;
2952 		(fas->f_tcmds[slot])++;
2953 		ASSERT(mutex_owned(FAS_MUTEX(fas)));
2969 		if (age >= fas->f_scsi_tag_age_limit &&
2973 			if (fas->f_reset_delay[Tgt(sp)] == 0) {
2974 				fas->f_throttle[slot] = DRAIN_THROTTLE;
2980 			tag = fas->f_active[slot]->f_tags;
2985 			if (++(fas->f_active[slot]->f_tags) >= NTAGS) {
2989 				fas->f_active[slot]->f_tags = 1;
3007 	fas_head_of_readyQ(fas, sp);
3020 fas_istart(struct fas *fas)
3026 	if (fas->f_state == STATE_FREE && fas->f_ncmds > fas->f_ndisc) {
3027 		(void) fas_ustart(fas);
3035 fas_ustart(struct fas *fas)
3038 	short slot = fas->f_next_slot;
3040 	short dslot = fas->f_dslot;
3043 	EPRINTF1("fas_ustart: start_slot=%x\n", fas->f_next_slot);
3044 	ASSERT(fas->f_current_sp == NULL);
3059 		if (fas->f_throttle[slot] == DRAIN_THROTTLE &&
3060 		    fas->f_tcmds[slot] == 0) {
3061 			fas_full_throttle(fas, slot);
3064 		if (fas->f_readyf[slot] &&
3065 		    (fas->f_throttle[slot] > fas->f_tcmds[slot])) {
3066 			sp = fas->f_readyf[slot];
3067 			fas->f_readyf[slot] = sp->cmd_forw;
3069 				fas->f_readyb[slot] = NULL;
3071 			fas->f_next_slot = NEXTSLOT(slot, dslot);
3075 			return (fas_startcmd(fas, sp));
3082 	fas->f_next_slot = NEXTSLOT(slot, dslot);
3092 fas_startcmd(struct fas *fas, struct fas_cmd *sp)
3094 	volatile struct fasreg *fasreg = fas->f_reg;
3098 	volatile uchar_t *tp = fas->f_cmdarea;
3101 	struct f_slots *slots = fas->f_active[slot];
3112 	ASSERT(fas->f_current_sp == NULL && fas->f_state == STATE_FREE);
3114 		ASSERT(fas->f_throttle[slot] > 0);
3115 		ASSERT(fas->f_reset_delay[Tgt(sp)] == 0);
3127 	    TAGGED(target) && fas->f_tcmds[slot] &&
3135 			if (fas->f_reset_delay[Tgt(sp)] == 0) {
3136 				fas->f_throttle[slot] = DRAIN_THROTTLE;
3138 			dp = fas->f_readyf[slot];
3139 			fas->f_readyf[slot] = sp;
3141 			if (fas->f_readyb[slot] == NULL) {
3142 				fas->f_readyb[slot] = sp;
3154 		if (fas_alloc_tag(fas, sp)) {
3163 			ASSERT(fas->f_active[slot]->f_slot[0] == NULL);
3164 			fas->f_active[slot]->f_slot[0] = sp;
3167 				ASSERT(fas->f_tcmds[slot] == 0);
3173 				fas->f_throttle[slot] = 1;
3175 			(fas->f_tcmds[slot])++;
3180 	fas->f_current_sp = sp;
3181 	fas->f_omsglen	= 0;
3183 	fas->f_sdtr_sent = fas->f_wdtr_sent =	0;
3187 		fas_force_renegotiation(fas, Tgt(sp));
3194 		LOAD_CMDP = fas->f_last_msgout = MSG_IDENTIFY | lun;
3197 		LOAD_CMDP = fas->f_last_msgout = MSG_DR_IDENTIFY | lun;
3207 	    ((fas->f_wide_known | fas->f_nowide) &
3208 	    (fas->f_sync_known | fas->f_nosync) & tshift)) {
3213 		fas->f_last_msgout = LOAD_CMDP = sp->cmd_tag[0];
3232 		fas->f_omsglen = sp->cmd_cdb[FAS_PROXY_DATA];
3233 		for (i = 0; i < (uint_t)fas->f_omsglen; i++) {
3234 			fas->f_cur_msgout[i] =
3245 	} else if (((fas->f_wide_known | fas->f_nowide) & tshift) == 0) {
3250 			fas->f_cur_msgout[i++] = sp->cmd_tag[0];
3251 			fas->f_cur_msgout[i++] = sp->cmd_tag[1];
3261 		fas_make_wdtr(fas, i, target, FAS_XFER_WIDTH);
3270 	} else if (((fas->f_sync_known | fas->f_nosync) & tshift) == 0) {
3278 			fas->f_cur_msgout[i++] = sp->cmd_tag[0];
3279 			fas->f_cur_msgout[i++] = sp->cmd_tag[1];
3282 		fas_make_sdtr(fas, i, target);
3310 	fas->f_lastcount = (uintptr_t)tp - (uintptr_t)fas->f_cmdarea;
3315 	fas_reg_write(fas, (uchar_t *)&fasreg->fas_busid,
3318 	FAS_SET_PERIOD_OFFSET_CONF3_REGS(fas, target);
3320 	fas_reg_cmd_write(fas, CMD_FLUSH);
3322 	FAS_DMA_READ(fas, fas->f_lastcount,
3323 	    fas->f_dmacookie.dmac_address, 16, cmd);
3325 	New_state(fas, (int)nstate);
3329 		fas_dump_cmd(fas, sp);
3338 		ASSERT(fas->f_tcmds[slot] >= 1);
3352 	fas_check_ncmds(fas);
3366 	struct fas *fas = (struct fas *)arg;
3373 		mutex_enter(FAS_MUTEX(fas));
3376 			if (fas_intr_svc(fas)) {
3383 				if (fas->f_polled_intr) {
3385 					fas->f_polled_intr = 0;
3390 		} while (INTPENDING(fas));
3392 		if (!kstat_updated && fas->f_intr_kstat &&
3394 			FAS_KSTAT_INTR(fas);
3401 		FAS_CHECK_WAITQ_AND_FAS_MUTEX_EXIT(fas);
3402 		FAS_EMPTY_CALLBACKQ(fas);
3404 	} while (INTPENDING(fas));
3417 fas_intr_svc(struct fas *fas)
3419 	static int (*evec[])(struct fas *fas) = {
3433 	volatile struct fasreg *fasreg = fas->f_reg;
3443 	fas->f_stat = fas_reg_read(fas, &fasreg->fas_stat);
3445 	EPRINTF2("fas_intr_svc: state=%x stat=%x\n", fas->f_state,
3446 	    fas->f_stat);
3451 	if ((fas->f_stat & FAS_STAT_IPEND) == 0) {
3452 		if (fas_check_dma_error(fas)) {
3462 	if (fas->f_state == ACTS_RESET) {
3472 	if ((fas->f_stat & FAS_STAT_GERR) &&
3473 	    (fas->f_stat & FAS_STAT_PERR) == 0) {
3474 		action = fas_handle_gross_err(fas);
3485 	fas->f_intr =
3486 	    intr = fas_reg_read(fas, (uchar_t *)&fasreg->fas_intr);
3492 	stat = fas->f_stat & FAS_PHASE_MASK;
3496 	    ((fas->f_state & STATE_SELECTING) == 0) &&
3497 	    (fas->f_state != ACTS_DATA_DONE) &&
3498 	    (fas->f_state != ACTS_C_CMPLT))) {
3500 		fas->f_stat2 = fas_reg_read(fas, &fasreg->fas_stat2);
3502 		if (((fas->f_stat2 & FAS_STAT2_EMPTY) == 0) ||
3503 		    (fas->f_stat2 & FAS_STAT2_ISHUTTLE)) {
3504 			fas_read_fifo(fas);
3508 	EPRINTF2("fas_intr_svc: intr=%x, stat=%x\n", fas->f_intr, fas->f_stat);
3509 	EPRINTF2("dmacsr=%b\n", fas->f_dma->dma_csr, dma_bits);
3535 		if (fas->f_state & STATE_SELECTING) {
3536 			action = fas_finish_select(fas);
3538 		} else if (fas->f_state & STATE_ITPHASES) {
3539 			action = fas_phasemanage(fas);
3542 			fas_log(fas, CE_WARN, "spurious interrupt");
3549 		if ((fas->f_state & STATE_SELECTING) == 0) {
3550 			ASSERT(fas->f_state == STATE_FREE);
3551 			action = fas_reconnect(fas);
3553 			action = fas_reselect_preempt(fas);
3557 		action = fas_illegal_cmd_or_bus_reset(fas);
3567 		    "fas_intr_svc call: fas 0x%p, action %d (%d)",
3568 		    fas, action, i);
3570 		action = (*evec[action])(fas);
3582 fas_phasemanage(struct fas *fas)
3586 	static int (*pvecs[])(struct fas *fas) = {
3609 		    fas_state_name(fas->f_state & STATE_ITPHASES));
3612 		    "fas_phasemanage_call: fas 0x%p (%d)", fas, i++);
3614 		state = fas->f_state;
3618 			action = (*pvecs[state-1]) (fas);
3620 			fas_log(fas, CE_WARN, "lost state in phasemanage");
3637 fas_remove_cmd(struct fas *fas, struct fas_cmd *sp, int new_timeout_flag)
3641 	struct f_slots *tag_slots = fas->f_active[slot];
3649 		fas->f_tcmds[slot]--;
3651 	if (fas->f_current_sp == sp) {
3652 		fas->f_current_sp = NULL;
3655 	ASSERT(sp != fas->f_active[sp->cmd_slot]->f_slot[sp->cmd_tag[1]]);
3674 			if (fas->f_tcmds[slot]) {
3705 	ASSERT(fas->f_ncmds >= fas->f_ndisc);
3712 fas_decrement_ncmds(struct fas *fas, struct fas_cmd *sp)
3716 		fas->f_ncmds--;
3718 			fas->f_ndisc--;
3723 	ASSERT((fas->f_ncmds >= 0) && (fas->f_ndisc >= 0));
3724 	ASSERT(fas->f_ncmds >= fas->f_ndisc);
3733 fas_finish(struct fas *fas)
3735 	struct fas_cmd *sp = fas->f_current_sp;
3754 	fas_reg_cmd_write(fas, CMD_EN_RESEL);
3765 		fas_force_renegotiation(fas, Tgt(sp));
3772 		fas_sync_wide_backoff(fas, sp, sp->cmd_slot);
3785 	fas_check_ncmds(fas);
3786 	fas_remove_cmd(fas, sp, NEW_TIMEOUT);
3787 	fas_decrement_ncmds(fas, sp);
3788 	fas_check_ncmds(fas);
3793 	New_state(fas, STATE_FREE);
3795 	if ((fas->f_ncmds > fas->f_ndisc) && (*((char *)status) == 0) &&
3796 	    (INTPENDING(fas) == 0)) {
3797 		if (fas_ustart(fas)) {
3819 		fas_call_pkt_comp(fas, sp);
3828 			if (fas_handle_sts_chk(fas, sp)) {
3838 			fas_handle_qfull(fas, sp);
3855 			fas_call_pkt_comp(fas, sp);
3867 fas_finish_select(struct fas *fas)
3869 	volatile struct dma *dmar = fas->f_dma;
3870 	struct fas_cmd *sp = fas->f_current_sp;
3871 	uchar_t intr = fas->f_intr;
3874 	step = fas_reg_read(fas, &fas->f_reg->fas_step) & FAS_STEP_MASK;
3884 	if ((fas->f_dma_csr = fas_dma_reg_read(fas, &dmar->dma_csr))
3891 		fas_log(fas, CE_WARN,
3893 		fas_set_pkt_reason(fas, sp, CMD_TRAN_ERR, 0);
3903 	FAS_FLUSH_DMA(fas);
3966 			fas_log(fas, CE_WARN,
3982 		New_state(fas, ACTS_UNKNOWN);
3985 		return (fas_handle_unknown(fas));
3992 		fas_force_renegotiation(fas, Tgt(sp));
3994 		fas->f_sdtr_sent = fas->f_wdtr_sent = 0;
4003 		if (fas->f_reset_delay[Tgt(sp)] == 0) {
4004 			fas->f_throttle[sp->cmd_slot] = DRAIN_THROTTLE;
4007 		fas_set_pkt_reason(fas, sp, CMD_INCOMPLETE, 0);
4013 		fas_printstate(fas, "undetermined selection failure");
4027 fas_reselect_preempt(struct fas *fas)
4035 	struct fas_cmd *sp = fas->f_current_sp;
4040 	FAS_FLUSH_DMA(fas);
4045 	New_state(fas, STATE_FREE);
4046 	rval = fas_reconnect(fas);
4054 		fas->f_throttle[sp->cmd_slot] = 1;
4057 		fas_remove_cmd(fas, sp, NEW_TIMEOUT);
4063 	if (fas->f_wdtr_sent) {
4064 		fas->f_wide_known &= ~(1<<Tgt(sp));
4065 		fas->f_wdtr_sent = 0;
4067 	if (fas->f_sdtr_sent) {
4068 		fas->f_sync_known &= ~(1<<Tgt(sp));
4069 		fas->f_sdtr_sent = 0;
4072 	fas_head_of_readyQ(fas, sp);
4081 fas_reconnect(struct fas *fas)
4083 	volatile struct fasreg *fasreg = fas->f_reg;
4094 	fas_check_ncmds(fas);
4096 	switch (fas->f_state) {
4104 		target = fas->f_fifo[0];
4110 		FAS_SET_PERIOD_OFFSET_CONF3_REGS(fas, target);
4118 		fas_reg_cmd_write(fas, CMD_MSG_ACPT);
4120 		if (fas->f_fifolen != 2) {
4129 		New_state(fas, ACTS_RESEL);
4131 		if (fas->f_stat & FAS_STAT_PERR) {
4138 		tmp = fas->f_fifo[1];
4139 		fas->f_last_msgin = tmp;
4151 		fas->f_resel_slot = slot = (target * NLUNS_PER_TARGET) | lun;
4153 		fas_reg_write(fas, (uchar_t *)&fasreg->fas_busid,
4163 		if (TAGGED(target) && fas->f_tcmds[slot] &&
4164 		    (fas->f_active[slot]->f_slot[0] == NULL)) {
4166 			    (uchar_t *)fas->f_cmdarea;
4179 			FAS_DMA_WRITE_SETUP(fas, 2,
4180 			    fas->f_dmacookie.dmac_address);
4188 			if (INTPENDING(fas) == 0) {
4196 			fas->f_stat = fas_reg_read(fas, &fasreg->fas_stat);
4197 			fas->f_intr = fas_reg_read(fas, &fasreg->fas_intr);
4198 			if (fas->f_intr & (FAS_INT_ILLEGAL | FAS_INT_RESET)) {
4199 				return (fas_illegal_cmd_or_bus_reset(fas));
4202 			if ((fas->f_stat & FAS_PHASE_MASK) !=
4208 			if (fas->f_intr & FAS_INT_DISCON) {
4213 			fas->f_current_sp = sp = fas->f_active[slot]->f_slot[0];
4221 			    (uchar_t *)fas->f_cmdarea;
4226 			slot = fas->f_resel_slot;
4229 			if ((fas->f_stat & FAS_PHASE_MASK) !=
4232 				if (fas->f_intr & ~(FAS_INT_BUS |
4234 					New_state(fas, ACTS_UNKNOWN);
4244 			fas_reg_cmd_write(fas, CMD_TRAN_INFO|CMD_DMA);
4245 			fas_dma_reg_write(fas, &fas->f_dma->dma_csr,
4246 			    fas->f_dma_csr);
4248 			fas_reg_cmd_write(fas, CMD_MSG_ACPT);
4256 				if (INTPENDING(fas)) {
4257 					fas->f_stat = fas_reg_read(fas,
4258 					    (uchar_t *)&fas->f_reg->fas_stat);
4259 					fas->f_intr = fas_reg_read(fas,
4260 					    (uchar_t *)&fas->f_reg->fas_intr);
4261 					if (fas->f_intr & (FAS_INT_RESET |
4265 						    (fas));
4267 					if (fas->f_intr & FAS_INT_FCMP) {
4278 			FAS_FLUSH_DMA(fas);
4296 			if (fas->f_stat & FAS_STAT_PERR) {
4300 			if ((fas->f_stat & FAS_STAT_XZERO) == 0 ||
4315 			tag_slots = fas->f_active[slot];
4323 			fas->f_current_sp = sp;
4327 	if (fas->f_stat & FAS_STAT_PERR) {
4367 		fas_assert_atn(fas);
4368 		fas->f_omsglen = sp->cmd_cdb[FAS_PROXY_DATA];
4370 		while (tmp < fas->f_omsglen) {
4371 			fas->f_cur_msgout[tmp] =
4381 		fas->f_ndisc++;
4382 		ASSERT((fas->f_ncmds >= 0) && (fas->f_ndisc >= 0));
4383 		ASSERT(fas->f_ncmds >= fas->f_ndisc);
4386 	ASSERT(fas->f_resel_slot == slot);
4387 	ASSERT(fas->f_ndisc > 0);
4388 	fas->f_ndisc--;
4390 	New_state(fas, ACTS_UNKNOWN);
4413 	if (sp && (fas->f_stat	& FAS_STAT_PERR)) {
4416 	fas_log(fas, CE_WARN, "target %x: failed reselection (%s)",
4420 	fas_printstate(fas, "failed reselection");
4433 fas_handle_unknown(struct fas *fas)
4436 	    "fas_handle_unknown_start: fas 0x%p", fas);
4439 	if ((fas->f_intr & FAS_INT_DISCON) == 0) {
4444 		switch (fas->f_stat & FAS_PHASE_MASK) {
4447 			New_state(fas, ACTS_DATA);
4451 			return (fas_handle_data_start(fas));
4454 			New_state(fas, ACTS_MSG_OUT);
4458 			return (fas_handle_msg_out_start(fas));
4461 			New_state(fas, ACTS_MSG_IN);
4465 			return (fas_handle_msg_in_start(fas));
4468 			fas_reg_cmd_write(fas, CMD_FLUSH);
4470 			if (fas_ptest_status & (1<<Tgt(fas->f_current_sp))) {
4471 				fas_assert_atn(fas);
4475 			fas_reg_cmd_write(fas, CMD_COMP_SEQ);
4476 			New_state(fas, ACTS_C_CMPLT);
4481 			return (fas_handle_c_cmplt(fas));
4484 			New_state(fas, ACTS_CMD_START);
4488 			return (fas_handle_cmd_start(fas));
4491 		fas_printstate(fas, "Unknown bus phase");
4510 		int msgout = fas->f_cur_msgout[0];
4511 		struct fas_cmd *sp = fas->f_current_sp;
4515 			msgout = fas->f_cur_msgout[2];
4518 		    fas->f_cur_msgout[0], fas->f_cur_msgout[1],
4519 		    fas->f_cur_msgout[2], fas->f_last_msgout);
4529 				fas->f_abort_msg_sent++;
4531 					fas_set_pkt_reason(fas, sp,
4535 				fas->f_reset_msg_sent++;
4537 					fas_set_pkt_reason(fas, sp,
4540 				fas_force_renegotiation(fas, target);
4543 			if ((fas->f_last_msgout == MSG_EXTENDED) &&
4544 			    (fas->f_last_msgin == MSG_REJECT)) {
4550 				New_state(fas, STATE_FREE);
4551 				fas_reg_cmd_write(fas, CMD_EN_RESEL);
4552 				fas_remove_cmd(fas, sp, NEW_TIMEOUT);
4553 				fas_decrement_ncmds(fas, sp);
4554 				fas_check_ncmds(fas);
4556 				(void) fas_accept_pkt(fas, sp,	NO_TRAN_BUSY);
4557 				fas_check_ncmds(fas);
4563 			} else if (fas->f_last_msgout == MSG_EXTENDED)	{
4568 				fas_reset_sync_wide(fas);
4569 				fas->f_sdtr_sent = fas->f_wdtr_sent = 0;
4572 			fas_set_pkt_reason(fas, sp, CMD_UNX_BUS_FREE, 0);
4574 			fas_printstate(fas, "unexpected bus free");
4589 fas_handle_clearing(struct fas *fas)
4591 	struct fas_cmd *sp = fas->f_current_sp;
4597 	if (fas->f_laststate == ACTS_C_CMPLT ||
4598 	    fas->f_laststate == ACTS_MSG_IN_DONE) {
4599 		if (INTPENDING(fas)) {
4600 			volatile struct fasreg *fasreg = fas->f_reg;
4602 			fas->f_stat = fas_reg_read(fas,
4604 			fas->f_intr = fas_reg_read(fas,
4606 			if (fas->f_intr & (FAS_INT_RESET | FAS_INT_ILLEGAL)) {
4607 				return (fas_illegal_cmd_or_bus_reset(fas));
4613 			fas->f_laststate = ACTS_CLEARING;
4621 	if (fas->f_intr == FAS_INT_DISCON) {
4630 		fas->f_last_msgout = 0xff;
4631 		fas->f_omsglen = 0;
4632 		if (fas->f_last_msgin == MSG_DISCONNECT) {
4634 			fas_reg_cmd_write(fas, CMD_EN_RESEL);
4636 			New_state(fas, STATE_FREE);
4638 			ASSERT(fas->f_current_sp != NULL);
4644 				fas->f_ndisc++;
4646 			ASSERT((fas->f_ncmds >= 0) && (fas->f_ndisc >= 0));
4647 			ASSERT(fas->f_ncmds >= fas->f_ndisc);
4649 			fas->f_current_sp = NULL;
4654 			if ((fas->f_ncmds > fas->f_ndisc) && fas_ustart(fas)) {
4669 			return (fas_finish(fas));
4678 		fas_log(fas, CE_WARN,
4680 		    Tgt(sp), scsi_mname(fas->f_last_msgin));
4682 		fas_set_pkt_reason(fas, sp, CMD_TRAN_ERR, 0);
4686 		    fas->f_cur_msgout[0], fas->f_cur_msgout[1],
4687 		    fas->f_cur_msgout[2], fas->f_last_msgout);
4688 		IPRINTF1("last msgin=%x\n", fas->f_last_msgin);
4700 fas_handle_data_start(struct fas *fas)
4704 	struct fas_cmd *sp = fas->f_current_sp;
4712 		fas_printstate(fas, "unexpected data phase");
4714 		fas_set_pkt_reason(fas, sp, CMD_TRAN_ERR, 0);
4724 		if (fas_restore_pointers(fas, sp)) {
4751 		if (fas_next_window(fas, sp, end)) {
4762 	if (fas->f_dma_attr->dma_attr_count_max < amt) {
4763 		amt = fas->f_dma_attr->dma_attr_count_max;
4772 	if ((end & ~fas->f_dma_attr->dma_attr_seg) !=
4773 	    (sp->cmd_cur_addr & ~fas->f_dma_attr->dma_attr_seg)) {
4776 		    sp->cmd_cur_addr, end, fas->f_dma_attr->dma_attr_seg);
4777 		amt = (end & ~fas->f_dma_attr->dma_attr_seg) - sp->cmd_cur_addr;
4778 		if (amt == 0 || amt > fas->f_dma_attr->dma_attr_count_max) {
4779 			fas_log(fas, CE_WARN, "illegal dma boundary? %x", amt);
4794 	fas->f_lastcount = amt;
4799 	phase = fas->f_stat & FAS_PHASE_MASK;
4802 		FAS_DMA_WRITE(fas, amt, sp->cmd_cur_addr,
4805 		FAS_DMA_READ(fas, amt, sp->cmd_cur_addr, amt,
4808 		fas_log(fas, CE_WARN,
4810 		fas_set_pkt_reason(fas, sp, CMD_DMA_DERR, 0);
4818 		fas_assert_atn(fas);
4822 	New_state(fas, ACTS_DATA_DONE);
4830 fas_handle_data_done(struct fas *fas)
4832 	volatile struct fasreg *fasreg = fas->f_reg;
4833 	volatile struct dma *dmar = fas->f_dma;
4834 	struct fas_cmd *sp = fas->f_current_sp;
4844 	stat = fas->f_stat;
4850 	if ((fas->f_dma_csr = fas_dma_reg_read(fas, &dmar->dma_csr)) &
4857 		fas_log(fas, CE_WARN, "Unrecoverable DMA error on dma %s",
4859 		fas_set_pkt_reason(fas, sp, CMD_TRAN_ERR, 0);
4882 			fas_log(fas, CE_WARN,
4884 			fas->f_cur_msgout[0] = MSG_INITIATOR_ERROR;
4885 			fas->f_omsglen = 1;
4891 	FAS_FLUSH_DMA(fas);
4899 	if (fas->f_intr != FAS_INT_BUS) {
4900 		New_state(fas, ACTS_UNKNOWN);
4911 	fifoamt = FIFO_CNT(fas);
4912 	if (fas->f_wide_enabled & (1<<tgt)) {
4917 		xfer_amt = fas->f_lastcount;
4920 		xfer_amt = fas->f_lastcount - xfer_amt;
4923 	    fifoamt, xfer_amt, fas->f_lastcount, stat);
4938 	 * the fas asserts an interrupt.
4947 	fas->f_stat2 = fas_reg_read(fas,
4950 	if (((fas->f_stat & FAS_STAT_XZERO) == 0) &&
4953 	    (fas->f_stat2 & FAS_STAT2_ISHUTTLE)) {
4954 		fas_log(fas, CE_WARN,
4956 		fas_set_pkt_reason(fas, sp, CMD_TRAN_ERR, 0);
4969 	if (fas->f_offset[tgt]) {
4976 			fas_reg_cmd_write(fas, CMD_FLUSH);
4982 		fas_reg_cmd_write(fas, CMD_FLUSH);
4993 	New_state(fas, ACTS_UNKNOWN);
4999 		fas->f_state = ACTS_DATA;
5003 		return (fas_handle_data_start(fas));
5008 	return (fas_handle_unknown(fas));
5014 fas_handle_c_cmplt(struct fas *fas)
5016 	struct fas_cmd *sp = fas->f_current_sp;
5017 	volatile struct fasreg *fasreg = fas->f_reg;
5029 	if (fas->f_laststate == ACTS_UNKNOWN) {
5030 		if (INTPENDING(fas)) {
5031 			fas->f_stat = fas_reg_read(fas,
5033 			intr = fas_reg_read(fas, (uchar_t *)&fasreg->fas_intr);
5034 			fas->f_intr = intr;
5035 			if (fas->f_intr & (FAS_INT_RESET | FAS_INT_ILLEGAL)) {
5036 				return (fas_illegal_cmd_or_bus_reset(fas));
5042 			fas->f_laststate = ACTS_C_CMPLT;
5049 		intr = fas->f_intr;
5055 		fas->f_stat |= FAS_STAT_PERR;
5062 		fas->f_stat |= FAS_STAT_PERR;
5070 		New_state(fas, ACTS_UNKNOWN);
5073 		return (fas_handle_unknown(fas));
5076 	if ((perr = (fas->f_stat & FAS_STAT_PERR)) != 0) {
5077 		fas_assert_atn(fas);
5096 		    sts = fas_reg_read(fas, (uchar_t *)&fasreg->fas_fifo_data);
5097 		fas->f_last_msgin = fas->f_imsgarea[0] =
5098 		    msg = fas_reg_read(fas, (uchar_t *)&fasreg->fas_fifo_data);
5100 		fas_reg_cmd_write(fas, CMD_MSG_ACPT);
5114 			fas_log(fas, CE_WARN, msginperr);
5117 			fas->f_cur_msgout[0] = MSG_MSG_PARITY;
5118 			fas->f_omsglen = 1;
5119 			New_state(fas, ACTS_UNKNOWN);
5130 		sts = fas_reg_read(fas, (uchar_t *)&fasreg->fas_fifo_data);
5143 			fas_log(fas, CE_WARN,
5145 			fas->f_cur_msgout[0] = MSG_INITIATOR_ERROR;
5146 			fas->f_omsglen = 1;
5147 			New_state(fas, ACTS_UNKNOWN);
5151 			return (fas_handle_unknown(fas));
5157 		New_state(fas, ACTS_UNKNOWN);
5160 		return (fas_handle_unknown(fas));
5172 		New_state(fas, ACTS_CLEARING);
5176 		return (fas_handle_clearing(fas));
5178 		fas->f_imsglen = 1;
5179 		fas->f_imsgindex = 1;
5180 		New_state(fas, ACTS_MSG_IN_DONE);
5184 		return (fas_handle_msg_in_done(fas));
5192 fas_handle_msg_in_start(struct fas *fas)
5203 	if (!FIFO_EMPTY(fas)) {
5204 		fas_reg_cmd_write(fas, CMD_FLUSH);
5206 	fas_reg_cmd_write(fas, CMD_TRAN_INFO);
5207 	fas->f_imsglen = 1;
5208 	fas->f_imsgindex = 0;
5209 	New_state(fas, ACTS_MSG_IN_DONE);
5234 fas_handle_more_msgin(struct fas *fas)
5240 	if (fas->f_intr & FAS_INT_BUS) {
5241 		if ((fas->f_stat & FAS_PHASE_MASK) == FAS_PHASE_MSG_IN) {
5245 			fas_reg_cmd_write(fas, CMD_TRAN_INFO);
5246 			New_state(fas, ACTS_MSG_IN_DONE);
5263 		if (fas->f_imsglen != 0) {
5264 			fas_log(fas, CE_WARN,
5268 	New_state(fas, ACTS_UNKNOWN);
5271 	return (fas_handle_unknown(fas));
5275 fas_handle_msg_in_done(struct fas *fas)
5277 	struct fas_cmd *sp = fas->f_current_sp;
5278 	volatile struct fasreg *fasreg = fas->f_reg;
5285 	if (fas->f_laststate == ACTS_MSG_IN) {
5286 		if (INTPENDING(fas)) {
5287 			fas->f_stat = fas_reg_read(fas,
5289 			fas->f_stat2 = fas_reg_read(fas,
5292 			fas_read_fifo(fas);
5294 			fas->f_intr = fas_reg_read(fas,
5296 			if (fas->f_intr & (FAS_INT_RESET | FAS_INT_ILLEGAL)) {
5297 				return (fas_illegal_cmd_or_bus_reset(fas));
5303 			fas->f_laststate = ACTS_MSG_IN_DONE;
5317 	if (((fas->f_laststate == ACTS_MSG_IN) ||
5318 	    (fas->f_laststate == ACTS_MSG_IN_DONE)) &&
5319 	    ((fas->f_intr & FAS_INT_DISCON) == 0) &&
5320 	    ((fas->f_stat & FAS_STAT_PERR) == 0) &&
5323 		if ((fas->f_fifolen == 1) &&
5324 		    (fas->f_imsglen == 1) &&
5325 		    (fas->f_fifo[0] == MSG_DISCONNECT)) {
5327 			fas_reg_cmd_write(fas, CMD_MSG_ACPT);
5328 			fas->f_imsgarea[fas->f_imsgindex++] = fas->f_fifo[0];
5329 			fas->f_last_msgin = MSG_DISCONNECT;
5330 			New_state(fas, ACTS_CLEARING);
5336 			return (fas_handle_clearing(fas));
5354 	if (fas->f_laststate != ACTS_C_CMPLT) {
5359 		if (fas->f_intr & FAS_INT_DISCON) {
5360 			fas_log(fas, CE_WARN,
5362 			New_state(fas, ACTS_UNKNOWN);
5374 		if (fas->f_imsglen != 0 && (fas->f_stat & FAS_STAT_PERR)) {
5375 			fas_log(fas, CE_WARN, msginperr);
5378 			fas_reg_cmd_write(fas, CMD_FLUSH);
5380 		} else if ((msgin = fas->f_fifolen) != 1) {
5387 			fas_printf(fas, "fifocount=%x", msgin);
5388 			fas_printstate(fas, "input message botch");
5390 			fas_reg_cmd_write(fas, CMD_FLUSH);
5391 			fas_log(fas, CE_WARN, "input message botch");
5393 		} else if (fas->f_imsglen == 0) {
5399 			msgin = fas_reg_read(fas,
5401 			New_state(fas, ACTS_MSG_IN_MORE);
5404 			msgin = fas->f_fifo[0];
5405 			fas->f_imsgarea[fas->f_imsgindex++] = msgin;
5414 		msgin = fas->f_imsgarea[0];
5422 	if (sndmsg == 0 && fas->f_imsglen != 0) {
5424 		if (fas->f_imsgindex < fas->f_imsglen) {
5427 			    fas->f_imsgindex-1,
5428 			    fas->f_imsgarea[fas->f_imsgindex-1]);
5430 			New_state(fas, ACTS_MSG_IN_MORE);
5432 		} else if (fas->f_imsglen == 1) {
5439 				fas_assert_atn(fas);
5440 				fas->f_stat |= FAS_STAT_PERR;
5441 				fas->f_imsgindex -= 1;
5449 			sndmsg = fas_onebyte_msg(fas);
5451 		} else if (fas->f_imsglen == 2) {
5455 				fas_assert_atn(fas);
5456 				fas->f_stat |= FAS_STAT_PERR;
5457 				fas->f_imsgindex -= 1;
5465 			if (fas->f_imsgarea[0] ==  MSG_EXTENDED) {
5474 					fas_log(fas, CE_WARN,
5475 					    tool, fas->f_imsgarea[0]);
5478 					fas->f_imsglen = msgin + 2;
5479 					New_state(fas, ACTS_MSG_IN_MORE);
5482 				sndmsg = fas_twobyte_msg(fas);
5486 			sndmsg = fas_multibyte_msg(fas);
5502 			fas->f_omsglen = 1;
5504 		fas->f_cur_msgout[0] = (uchar_t)sndmsg;
5527 		fas_assert_atn(fas);
5528 		New_state(fas, ACTS_MSG_IN_MORE);
5529 		fas->f_imsglen = 0;
5532 	fas_reg_cmd_write(fas, CMD_FLUSH);
5534 	fas_reg_cmd_write(fas, CMD_MSG_ACPT);
5536 	if ((fas->f_laststate == ACTS_MSG_IN_DONE) &&
5537 	    (fas->f_state == ACTS_CLEARING)) {
5540 		return (fas_handle_clearing(fas));
5548 fas_onebyte_msg(struct fas *fas)
5550 	struct fas_cmd *sp = fas->f_current_sp;
5552 	uchar_t msgin = fas->f_last_msgin = fas->f_imsgarea[0];
5573 		fas_log(fas, CE_WARN, "%s message 0x%x from Target %d",
5583 			New_state(fas, ACTS_UNKNOWN);
5588 		fas->f_imsglen = 2;
5589 		New_state(fas, ACTS_MSG_IN_MORE);
5593 	New_state(fas, ACTS_UNKNOWN);
5609 		fas->f_state = ACTS_CLEARING;
5619 		uchar_t lastmsg = fas->f_last_msgout;
5638 			if (fas->f_wdtr_sent) {
5643 				fas_set_wide_conf3(fas, tgt, 0);
5644 				fas->f_nowide |= (1<<tgt);
5645 				fas->f_wdtr_sent = 0;
5649 				if ((fas->f_nosync & (1<<tgt)) == 0) {
5650 					fas_assert_atn(fas);
5651 					fas_make_sdtr(fas, 0, tgt);
5653 			} else if (fas->f_sdtr_sent) {
5654 				fas_reg_cmd_write(fas, CMD_CLR_ATN);
5655 				fas_revert_to_async(fas, tgt);
5656 				fas->f_nosync |= (1<<tgt);
5657 				fas->f_sdtr_sent = 0;
5713 			fas_log(fas, CE_WARN,
5716 			fas_set_pkt_reason(fas, sp, reason, 0);
5724 			if (fas_restore_pointers(fas, sp)) {
5749 		fas_log(fas, CE_WARN,
5764 fas_handle_cmd_start(struct fas *fas)
5766 	struct fas_cmd *sp = fas->f_current_sp;
5767 	volatile uchar_t *tp = fas->f_cmdarea;
5778 	fas_reg_cmd_write(fas, CMD_FLUSH);
5780 	FAS_DMA_READ(fas, amt, fas->f_dmacookie.dmac_address, amt,
5782 	fas->f_lastcount = amt;
5784 	New_state(fas, ACTS_CMD_DONE);
5792 fas_handle_cmd_done(struct fas *fas)
5794 	struct fas_cmd *sp = fas->f_current_sp;
5795 	uchar_t intr = fas->f_intr;
5796 	volatile struct dma *dmar = fas->f_dma;
5809 			fas_printstate(fas, "cmd transmission error");
5819 	fas->f_dma_csr = fas_dma_reg_read(fas, &dmar->dma_csr);
5820 	FAS_FLUSH_DMA(fas);
5822 	New_state(fas, ACTS_UNKNOWN);
5825 	return (fas_handle_unknown(fas));
5832 fas_handle_msg_out_start(struct fas *fas)
5834 	struct fas_cmd *sp = fas->f_current_sp;
5835 	uchar_t *msgout = fas->f_cur_msgout;
5836 	uchar_t amt = fas->f_omsglen;
5852 	if ((fas->f_stat & FAS_PHASE_MASK) != FAS_PHASE_MSG_OUT &&
5853 	    fas->f_laststate == ACTS_MSG_OUT_DONE) {
5854 		fas_log(fas, CE_WARN,
5856 		fas_set_pkt_reason(fas, sp, CMD_NOMSGOUT, 0);
5857 		New_state(fas, ACTS_UNKNOWN);
5866 	fas_reg_cmd_write(fas, CMD_FLUSH);
5873 		amt = fas->f_omsglen = 1;
5881 	fas->f_last_msgout = *msgout;
5890 	fas_write_fifo(fas, msgout, fas->f_omsglen, 1);
5891 	fas_reg_cmd_write(fas, CMD_TRAN_INFO);
5893 	EPRINTF2("amt=%x, last_msgout=%x\n", amt, fas->f_last_msgout);
5895 	New_state(fas, ACTS_MSG_OUT_DONE);
5902 fas_handle_msg_out_done(struct fas *fas)
5904 	struct fas_cmd *sp = fas->f_current_sp;
5907 	int	amt = fas->f_omsglen;
5912 	msgout = fas->f_cur_msgout[0];
5914 		msgout = fas->f_cur_msgout[2];
5917 	    fas->f_cur_msgout[0], fas->f_cur_msgout[1],
5918 	    fas->f_cur_msgout[2], fas->f_last_msgout);
5925 	fas_reg_cmd_write(fas, CMD_FLUSH);
5931 	if (fas->f_intr == FAS_INT_DISCON) {
5940 				fas->f_abort_msg_sent++;
5942 					fas_set_pkt_reason(fas, sp,
5946 				fas->f_reset_msg_sent++;
5948 					fas_set_pkt_reason(fas, sp,
5951 				fas_force_renegotiation(fas, Tgt(sp));
5975 	phase = fas->f_stat & FAS_PHASE_MASK;
5984 	if ((fas->f_intr & FAS_INT_BUS) && phase == FAS_PHASE_MSG_OUT) {
5991 			fas_assert_atn(fas);
5993 		fas_log(fas, CE_WARN,
5996 		New_state(fas, ACTS_MSG_OUT);
6005 	fas->f_last_msgout = msgout;
6006 	fas->f_omsglen = 0;
6007 	New_state(fas, ACTS_UNKNOWN);
6008 	action = fas_handle_unknown(fas);
6015 fas_twobyte_msg(struct fas *fas)
6017 	struct fas_cmd *sp = fas->f_current_sp;
6019 	if ((fas->f_imsgarea[0] == MSG_IGNORE_WIDE_RESID) &&
6020 	    (fas->f_imsgarea[1] == 1)) {
6033 		IPRINTF1("ignore wide resid %d\n", fas->f_imsgarea[1]);
6034 		New_state(fas, ACTS_UNKNOWN);
6038 	fas_log(fas, CE_WARN,
6040 	    scsi_mname(fas->f_imsgarea[0]), fas->f_imsgarea[1]);
6048 fas_multibyte_msg(struct fas *fas)
6058 	struct fas_cmd *sp = fas->f_current_sp;
6059 	volatile struct fasreg *fasreg = fas->f_reg;
6060 	uchar_t emsg = fas->f_imsgarea[2];
6071 		period = fas->f_imsgarea[3] & 0xff;
6072 		offset = fas->f_imsgarea[4] & 0xff;
6073 		minsync = MIN_SYNC_PERIOD(fas);
6074 		maxsync = MAX_SYNC_PERIOD(fas);
6076 		    fas->f_imsgarea[0], fas->f_imsgarea[1],
6077 		    fas->f_imsgarea[2], fas->f_imsgarea[3],
6078 		    fas->f_imsgarea[4]);
6084 		    fas->f_sync_period[tgt], fas->f_neg_period[tgt]);
6086 		if ((++(fas->f_sdtr_sent)) & 1) {
6103 			    period ? max(period, MIN_SYNC_PERIOD(fas)) : 0;
6105 			if (fas->f_backoff & (1<<tgt)) {
6107 				    max(period, fas->f_neg_period[tgt]) : 0;
6149 			clockval = fas->f_clock_cycle / 1000;
6161 		fas->f_offset[tgt] = offset;
6162 		fas->f_neg_period[tgt] = period;
6169 			fas_make_sdtr(fas, 0, tgt);
6170 			period = fas->f_neg_period[tgt];
6171 			offset = (fas->f_offset[tgt] & 0xf);
6175 			fas->f_sync_period[tgt] = regval & SYNC_PERIOD_MASK;
6176 			fas_reg_write(fas, (uchar_t *)&fasreg->fas_sync_period,
6177 			    fas->f_sync_period[tgt]);
6179 			fas->f_offset[tgt] = offset | fas->f_req_ack_delay;
6180 			fas_reg_write(fas, (uchar_t *)&fasreg->fas_sync_offset,
6181 			    fas->f_offset[tgt]);
6188 				fas->f_fasconf3[tgt] |= FAS_CONF3_FASTSCSI;
6190 				fas->f_fasconf3[tgt] &= ~FAS_CONF3_FASTSCSI;
6193 			fas_reg_write(fas, (uchar_t *)&fasreg->fas_conf3,
6194 			    fas->f_fasconf3[tgt]);
6198 			    fas->f_sync_period[tgt] & SYNC_PERIOD_MASK,
6199 			    fas->f_offset[tgt] & 0xf, tgt);
6200 			DPRINTF1("req/ack delay = %x\n", fas->f_req_ack_delay);
6201 			DPRINTF1("conf3 = %x\n", fas->f_fasconf3[tgt]);
6210 			    fas->f_clock_cycle) / 1000);
6211 			xfer_rate = ((fas->f_nowide & (1<<tgt))? 1 : 2) *
6225 			fas->f_sync_enabled |= (1<<tgt);
6231 			fas_revert_to_async(fas, tgt);
6239 			fas->f_nosync |= (1<<tgt);
6242 		fas->f_props_update |= (1<<tgt);
6245 		uchar_t width = fas->f_imsgarea[3] & 0xff;
6248 		    fas->f_imsgarea[0], fas->f_imsgarea[1],
6249 		    fas->f_imsgarea[2], fas->f_imsgarea[3]);
6254 		if ((++(fas->f_wdtr_sent)) &	1) {
6261 			fas->f_nowide &= ~(1<<tgt);
6262 			fas_make_wdtr(fas, 0, tgt, width);
6271 			fas_revert_to_async(fas, tgt);
6272 			fas->f_sync_known &= ~(1<<tgt);
6277 			fas_set_wide_conf3(fas, tgt, width);
6279 			fas->f_wdtr_sent = 0;
6280 			if ((fas->f_nosync & (1<<tgt)) == 0) {
6281 				fas_make_sdtr(fas, 0, tgt);
6287 		fas->f_props_update |= (1<<tgt);
6292 		fas_log(fas, CE_WARN,
6298 	New_state(fas, ACTS_UNKNOWN);
6307 fas_revert_to_async(struct fas *fas, int tgt)
6309 	volatile struct fasreg *fasreg = fas->f_reg;
6311 	fas->f_sync_period[tgt] = 0;
6312 	fas_reg_write(fas, (uchar_t *)&fasreg->fas_sync_period, 0);
6313 	fas->f_offset[tgt] = 0;
6314 	fas_reg_write(fas, (uchar_t *)&fasreg->fas_sync_offset, 0);
6315 	fas->f_fasconf3[tgt] &= ~FAS_CONF3_FASTSCSI;
6316 	fas_reg_write(fas, &fasreg->fas_conf3, fas->f_fasconf3[tgt]);
6317 	fas->f_sync_enabled &= ~(1<<tgt);
6325 fas_handle_selection(struct fas *fas)
6327 	fas_reg_cmd_write(fas, CMD_DISCONNECT);
6328 	fas_reg_cmd_write(fas, CMD_FLUSH);
6329 	fas_reg_cmd_write(fas, CMD_EN_RESEL);
6337 fas_restore_pointers(struct fas *fas, struct fas_cmd *sp)
6345 			if (fas_set_new_window(fas, sp)) {
6355 fas_set_new_window(struct fas *fas, struct fas_cmd *sp)
6374 fas_next_window(struct fas *fas, struct fas_cmd *sp, uint64_t end)
6391 		if (fas_set_new_window(fas, sp)) {
6392 			fas_printstate(fas, "cannot set new window");
6402 		fas_printstate(fas, "data transfer overrun");
6403 		fas_set_pkt_reason(fas, sp, CMD_DATA_OVR, 0);
6410 		fas_sync_wide_backoff(fas, sp, slot);
6422 fas_check_dma_error(struct fas *fas)
6427 	if (fas->f_dma->dma_csr & DMA_ERRPEND) {
6433 		fas_log(fas, CE_WARN, "Unrecoverable DMA error");
6434 		fas_printstate(fas, "dma error");
6435 		fas_set_pkt_reason(fas, fas->f_current_sp, CMD_TRAN_ERR, 0);
6445 fas_handle_gross_err(struct fas *fas)
6447 	volatile struct fasreg *fasreg = fas->f_reg;
6449 	fas_log(fas, CE_WARN,
6450 	"gross error in fas status (%x)", fas->f_stat);
6453 	    fasreg->fas_cmd, fas->f_stat, fas->f_intr, fasreg->fas_step,
6456 	fas_set_pkt_reason(fas, fas->f_current_sp, CMD_TRAN_ERR, 0);
6458 	fas_internal_reset(fas, FAS_RESET_FAS);
6467 fas_illegal_cmd_or_bus_reset(struct fas *fas)
6474 	ASSERT(fas->f_intr & (FAS_INT_ILLEGAL | FAS_INT_RESET));
6476 	if (fas->f_intr & FAS_INT_RESET) {
6481 	 * Illegal cmd to fas:
6487 	if (fas->f_intr & FAS_INT_ILLEGAL) {
6488 		IPRINTF1("lastcmd=%x\n", fas->f_reg->fas_cmd);
6489 		fas_printstate(fas, "ILLEGAL bit set");
6500 fas_set_throttles(struct fas *fas, int slot, int n, int what)
6511 	if (fas->f_softstate & (FAS_SS_QUIESCED | FAS_SS_DRAINING)) {
6523 			fas->f_throttle[i] = HOLD_THROTTLE;
6524 		} else if ((fas->f_reset_delay[i/NLUNS_PER_TARGET]) == 0) {
6527 				fas->f_throttle[i] = (short)
6528 				    ((fas->f_notag & tshift)? 1 : what);
6530 				fas->f_throttle[i] = what;
6537 fas_set_all_lun_throttles(struct fas *fas, int slot, int what)
6542 	fas_set_throttles(fas, slot, NLUNS_PER_TARGET, what);
6546 fas_full_throttle(struct fas *fas, int slot)
6548 	fas_set_throttles(fas, slot, 1, MAX_THROTTLE);
6555 fas_runpoll(struct fas *fas, short slot, struct fas_cmd *sp)
6562 	    (void *)fas->f_current_sp, fas->f_tcmds[slot]);
6572 			fas_set_all_lun_throttles(fas, slot, HOLD_THROTTLE);
6574 		if ((fas->f_state != STATE_FREE) || INTPENDING(fas)) {
6575 			if (fas_dopoll(fas, POLL_TIMEOUT) <= 0) {
6581 		ASSERT(fas->f_state == STATE_FREE);
6582 		ASSERT(fas->f_current_sp == NULL);
6597 			if ((fas->f_tcmds[slot]) &&
6606 					fas_log(fas, CE_WARN,
6627 		if (fas->f_reset_delay[slot/NLUNS_PER_TARGET]) {
6629 			drv_usecwait(fas->f_scsi_reset_delay * 1000);
6631 				if (fas->f_reset_delay[i]) {
6634 					fas->f_reset_delay[i] = 0;
6636 						fas_full_throttle(fas, s);
6646 		if (fas_startcmd(fas, sp) != TRUE) {
6648 			ASSERT(fas->f_current_sp != sp);
6656 		 * fas->f_state is STATE_FREE, and
6670 			if ((n = fas_dopoll(fas, limit)) <= 0) {
6690 			ASSERT(fas->f_state == STATE_FREE);
6723 		fas_set_all_lun_throttles(fas, slot, MAX_THROTTLE);
6729 	fas_remove_cmd(fas, sp, 0);
6734 	if ((fas->f_state == STATE_FREE) &&
6736 		(void) fas_ustart(fas);
6743 	fas_log(fas, CE_WARN, "Polled cmd failed");
6745 	fas_printstate(fas, "fas_runpoll: polled cmd failed");
6749 	fas_set_all_lun_throttles(fas, slot, MAX_THROTTLE);
6755 	fas_remove_cmd(fas, sp, NEW_TIMEOUT);
6756 	fas_decrement_ncmds(fas, sp);
6757 	fas_set_pkt_reason(fas, sp, CMD_TRAN_ERR, 0);
6760 		(void) fas_reset_bus(fas);
6773 fas_dopoll(struct fas *fas, int limit)
6791 		if (INTPENDING(fas)) {
6792 			fas->f_polled_intr = 1;
6794 			(void) fas_intr_svc(fas);
6795 			if (fas->f_state == STATE_FREE)
6801 	if (i >= limit && fas->f_state != STATE_FREE) {
6802 		fas_printstate(fas, "polled command timeout");
6814 fas_make_sdtr(struct fas *fas, int msgout_offset, int target)
6816 	uchar_t *p = fas->f_cur_msgout + msgout_offset;
6818 	uchar_t period = MIN_SYNC_PERIOD(fas);
6827 	if (fas->f_backoff & tshift) {
6828 		period = fas->f_neg_period[target];
6835 	if (fas->f_sdtr_sent & 1) {
6836 		period = fas->f_neg_period[target];
6837 		offset = fas->f_offset[target];
6844 	if (fas->f_force_async & tshift) {
6851 	if (fas->f_target_scsi_options[target] & SCSI_OPTIONS_FAST) {
6855 	} else if (fas->f_target_scsi_options[target] & SCSI_OPTIONS_SYNC) {
6860 		fas->f_nosync |= tshift;
6863 	if (fas->f_nosync & tshift) {
6868 		offset = fas_default_offset | fas->f_req_ack_delay;
6871 	fas->f_neg_period[target] = (uchar_t)period;
6872 	fas->f_offset[target] = (uchar_t)offset;
6879 	fas->f_omsglen = 5 + msgout_offset;
6887 	fas->f_sdtr_sent++;
6894 	fas->f_sync_known |= 1<<target;
6895 	fas->f_wide_known |= 1<<target;
6902 fas_make_wdtr(struct fas *fas, int msgout_offset, int target, int width)
6904 	uchar_t *p = fas->f_cur_msgout + msgout_offset;
6906 	if (((fas->f_target_scsi_options[target] & SCSI_OPTIONS_WIDE) == 0) ||
6907 	    (fas->f_nowide & (1<<target))) {
6908 		fas->f_nowide |= 1<<target;
6911 	if (fas->f_force_narrow & (1<<target)) {
6920 	fas->f_omsglen = 4 + msgout_offset;
6927 	fas->f_wdtr_sent++;
6933 	fas->f_wide_known |= 1<<target;
6935 	fas_set_wide_conf3(fas, target, width);
6943 fas_create_arq_pkt(struct fas *fas, struct scsi_address *ap)
6956 	if (fas->f_arq_pkt[slot] != 0) {
6981 	fas->f_arq_pkt[slot] = rqpktp;
6998 fas_delete_arq_pkt(struct fas *fas, struct scsi_address *ap)
7007 	if ((rqpktp = fas->f_arq_pkt[slot]) != NULL) {
7020 		fas->f_arq_pkt[slot] = 0;
7032 	struct fas *fas = ADDR2FAS(&pkt->pkt_address);
7042 	ASSERT(sp == fas->f_arq_pkt[slot]);
7044 	ASSERT(ssp != fas->f_active[sp->cmd_slot]->f_slot[sp->cmd_tag[1]]);
7063 		fas_sync_wide_backoff(fas, sp, slot);
7066 	fas_call_pkt_comp(fas, ssp);
7073 fas_handle_sts_chk(struct fas *fas, struct fas_cmd *sp)
7075 	struct fas_cmd *arqsp =	fas->f_arq_pkt[sp->cmd_slot];
7082 		fas_call_pkt_comp(fas, sp);
7090 	ASSERT(sp != fas->f_active[sp->cmd_slot]->f_slot[sp->cmd_tag[1]]);
7092 	    sp->cmd_slot, (void *)arqsp, (void *)fas->f_arq_pkt[sp->cmd_slot]);
7116 	fas_full_throttle(fas, sp->cmd_slot);
7117 	(void) fas_accept_pkt(fas, arqsp, NO_TRAN_BUSY);
7121 	fas_set_pkt_reason(fas, sp, CMD_TRAN_ERR, 0);
7122 	fas_log(fas, CE_WARN, "auto request sense failed\n");
7123 	fas_dump_cmd(fas, sp);
7124 	fas_call_pkt_comp(fas, sp);
7133 fas_handle_qfull(struct fas *fas, struct fas_cmd *sp)
7137 	if ((++sp->cmd_qfull_retries > fas->f_qfull_retries[Tgt(sp)]) ||
7138 	    (fas->f_qfull_retries[Tgt(sp)] == 0)) {
7150 		fas_set_all_lun_throttles(fas, slot, DRAIN_THROTTLE);
7151 		fas_call_pkt_comp(fas, sp);
7153 		if (fas->f_reset_delay[Tgt(sp)] == 0) {
7154 			fas->f_throttle[slot] =
7155 			    max((fas->f_tcmds[slot] - 2), 0);
7158 		    "retrying\n", Tgt(sp), Lun(sp), fas->f_throttle[slot]);
7161 		(void) fas_accept_pkt(fas, sp, NO_TRAN_BUSY);
7170 		if (fas->f_throttle[slot] == HOLD_THROTTLE) {
7177 			fas_set_all_lun_throttles(fas, slot, QFULL_THROTTLE);
7178 			if (fas->f_restart_cmd_timeid == 0) {
7179 				fas->f_restart_cmd_timeid =
7180 				    timeout(fas_restart_cmd, fas,
7181 				    fas->f_qfull_retry_interval[Tgt(sp)]);
7193 	struct fas *fas = fas_arg;
7198 	mutex_enter(FAS_MUTEX(fas));
7199 	fas->f_restart_cmd_timeid = 0;
7202 		if (fas->f_reset_delay[i/NLUNS_PER_TARGET] == 0) {
7203 			if (fas->f_throttle[i] == QFULL_THROTTLE) {
7204 				fas_set_all_lun_throttles(fas,
7210 	(void) fas_ustart(fas);
7211 	mutex_exit(FAS_MUTEX(fas));
7223 	struct fas *fas;
7228 	for (fas = fas_head; fas != (struct fas *)NULL; fas = fas->f_next) {
7230 		mutex_enter(FAS_MUTEX(fas));
7231 		IPRINTF2("ncmds=%x, ndisc=%x\n", fas->f_ncmds, fas->f_ndisc);
7234 	if (fas->f_total_cmds) {
7235 		int n = fas->f_total_cmds;
7237 		fas_log(fas, CE_NOTE,
7238 	"total=%d, cmds=%d fas-rd=%d, fas-wrt=%d, dma-rd=%d, dma-wrt=%d\n",
7239 		    fas->f_total_cmds,
7240 		    fas->f_reg_cmds/n,
7241 		    fas->f_reg_reads/n, fas->f_reg_writes/n,
7242 		    fas->f_reg_dma_reads/n, fas->f_reg_dma_writes/n);
7244 		fas->f_reg_reads = fas->f_reg_writes =
7245 		    fas->f_reg_dma_reads = fas->f_reg_dma_writes =
7246 		    fas->f_reg_cmds = fas->f_total_cmds = 0;
7249 		if (fas->f_ncmds) {
7251 			fas_watchsubr(fas);
7266 				if ((fas->f_throttle[i] > HOLD_THROTTLE) &&
7267 				    (fas->f_active[i] &&
7268 				    (fas->f_active[i]->f_slot[0] == NULL))) {
7269 					fas_full_throttle(fas, i);
7274 		if (fas->f_props_update) {
7279 			 * Hence we save the fas->f_props_update now and
7285 			props_update = fas->f_props_update;
7286 			fas->f_props_update = 0;
7289 					fas_update_props(fas, i);
7293 		fas_check_waitQ_and_mutex_exit(fas);
7308 fas_watchsubr(struct fas *fas)
7311 	int d = ((fas->f_dslot == 0)? 1 : fas->f_dslot);
7319 			(void) fas_reset_bus(fas);
7322 		if (fas_force_timeout && fas->f_tcmds[slot]) {
7323 			fas_cmd_timeout(fas, slot);
7327 		fas_test_reset(fas, slot);
7328 		fas_test_abort(fas, slot);
7334 		tag_slots = fas->f_active[slot];
7337 		    slot, fas->f_tcmds[slot], tag_slots->f_timeout);
7339 		if ((fas->f_tcmds[slot] > 0) && (tag_slots->f_timebase)) {
7351 				fas_cmd_timeout(fas, slot);
7359 				fas_set_throttles(fas, 0, N_SLOTS,
7370 fas_cmd_timeout(struct fas *fas, int slot)
7372 	int d = ((fas->f_dslot == 0)? 1 : fas->f_dslot);
7377 	ASSERT(fas->f_tcmds[slot]);
7389 		if (fas->f_throttle[i] == DRAIN_THROTTLE) {
7390 			fas_full_throttle(fas, i);
7395 		sp = fas->f_active[slot]->f_slot[0];
7402 	if (fas->f_current_sp && fas->f_state != STATE_FREE) {
7403 		for (i = 0; (i < 10000) && (INTPENDING(fas) == 0); i++) {
7406 		if (INTPENDING(fas) == 0) {
7407 			slot = fas->f_current_sp->cmd_slot;
7408 			sp = fas->f_current_sp;
7418 	n = fas->f_active[slot]->f_n_slots;
7420 		ssp = fas->f_active[slot]->f_slot[tag];
7422 			fas_set_pkt_reason(fas, ssp, CMD_TIMEOUT,
7424 			fas_short_dump_cmd(fas, ssp);
7441 			fas_log(fas, CE_WARN,
7445 			ASSERT(sp == fas->f_current_sp);
7446 			fas_log(fas, CE_WARN,
7453 			if (fas->f_state == ACTS_DATA_DONE) {
7454 				fas_sync_wide_backoff(fas, sp, slot);
7458 		fas_printstate(fas, "timeout");
7461 		fas_log(fas, CE_WARN,
7463 		    fas->f_tcmds[slot], target, lun);
7466 	if (fas_abort_cmd(fas, sp, slot) == ACTION_SEARCH) {
7467 		(void) fas_istart(fas);
7479 fas_sync_wide_backoff(struct fas *fas, struct fas_cmd *sp,
7483 	ushort_t state = fas->f_state;
7487 	phase = fas_reg_read(fas, &fas->f_reg->fas_stat);
7504 	if ((fas->f_backoff & tshift) ||
7505 	    (fas->f_nosync & tshift)) {
7509 		if ((fas->f_nowide & tshift) == 0) {
7510 			fas_log(fas, CE_WARN,
7519 		fas->f_target_scsi_options[tgt] &= ~SCSI_OPTIONS_WIDE;
7526 	if (fas->f_offset[tgt] != 0) {
7531 		if (fas->f_backoff & tshift) {
7532 			if ((fas->f_nosync & tshift) == 0) {
7533 				fas_log(fas, CE_WARN,
7537 			fas->f_target_scsi_options[tgt] &=
7541 			fas->f_neg_period[tgt] *= 2;
7543 			fas_log(fas, CE_WARN,
7547 	fas->f_backoff |= tshift;
7552 	if ((fas->f_fasconf & FAS_CONF_SLOWMODE) == 0) {
7553 		fas->f_fasconf |= FAS_CONF_SLOWMODE;
7554 		fas_reg_write(fas, &fas->f_reg->fas_conf, fas->f_fasconf);
7561 	fas_force_renegotiation(fas, tgt);
7562 	fas->f_props_update |= (1<<tgt);
7569 fas_reset_sync_wide(struct fas *fas)
7571 	struct fas_cmd *sp = fas->f_current_sp;
7574 	if (fas->f_wdtr_sent) {
7576 		fas->f_nowide |= (1<<tgt);
7577 		fas->f_fasconf3[tgt] &= ~FAS_CONF3_WIDE;
7578 		fas_reg_write(fas, &fas->f_reg->fas_conf3,
7579 		    fas->f_fasconf3[tgt]);
7584 		fas_reg_write(fas,
7585 		    (uchar_t *)&fas->f_reg->fas_sync_offset, 0);
7586 	} else if (fas->f_sdtr_sent) {
7588 		    fas->f_reg;
7590 		fas->f_nosync |= (1<<tgt);
7591 		fas->f_offset[tgt] = 0;
7592 		fas->f_sync_period[tgt] = 0;
7593 		fas_reg_write(fas,
7595 		fas_reg_write(fas,
7597 		fas->f_offset[tgt] = 0;
7598 		fas->f_fasconf3[tgt] &= ~FAS_CONF3_FASTSCSI;
7599 		fas_reg_write(fas, &fasreg->fas_conf3,
7600 		    fas->f_fasconf3[tgt]);
7603 	fas_force_renegotiation(fas, tgt);
7610 fas_force_renegotiation(struct fas *fas, int target)
7613 	fas->f_sync_known &= ~tshift;
7614 	fas->f_sync_enabled &= ~tshift;
7615 	fas->f_wide_known &= ~tshift;
7616 	fas->f_wide_enabled &= ~tshift;
7623 fas_set_wide_conf3(struct fas *fas, int target, int width)
7628 		fas->f_fasconf3[target] &= ~FAS_CONF3_WIDE;
7631 		fas->f_fasconf3[target] |= FAS_CONF3_WIDE;
7632 		fas->f_wide_enabled |= (1<<target);
7636 	fas_reg_write(fas, &fas->f_reg->fas_conf3, fas->f_fasconf3[target]);
7637 	fas->f_fasconf3_reg_last = fas->f_fasconf3[target];
7648 fas_abort_curcmd(struct fas *fas)
7650 	if (fas->f_current_sp) {
7651 		return (fas_abort_cmd(fas, fas->f_current_sp,
7652 		    fas->f_current_sp->cmd_slot));
7654 		return (fas_reset_bus(fas));
7659 fas_abort_cmd(struct fas *fas, struct fas_cmd *sp, int slot)
7663 	ap.a_hba_tran = fas->f_tran;
7674 	if ((fas->f_current_sp && (fas->f_current_sp->cmd_slot != slot)) ||
7675 	    (fas->f_state == STATE_FREE)) {
7691 	return (fas_reset_bus(fas));
7707 	struct fas *fas = ADDR2FAS(ap);
7711 	struct fas_cmd *cur_sp = fas->f_current_sp;
7724 	fas_move_waitQ_to_readyQ(fas);
7731 	ASSERT(mutex_owned(FAS_MUTEX(fas)));
7743 		rval = fas_remove_from_readyQ(fas, sp, slot);
7746 			fas_set_pkt_reason(fas, sp, CMD_ABORTED, STAT_ABORTED);
7747 			fas_decrement_ncmds(fas, sp);
7748 			fas_call_pkt_comp(fas, sp);
7752 		    fas->f_active[slot]->f_slot[sp->cmd_tag[1]])) {
7763 	fas_set_throttles(fas, slot, 1, HOLD_THROTTLE);
7785 		if ((sp == cur_sp) && (fas->f_state != STATE_FREE) &&
7787 			rval = fas_abort_connected_cmd(fas, sp, abort_msg);
7794 			rval = fas_abort_disconnected_cmd(fas, ap, sp,
7800 			fas_set_pkt_reason(fas, sp, CMD_ABORTED, STAT_ABORTED);
7811 		if (cur_sp && (fas->f_state != STATE_FREE) &&
7814 			rval = fas_abort_connected_cmd(fas, cur_sp,
7818 			rval = fas_abort_disconnected_cmd(fas, ap,
7828 			fas_remove_cmd(fas, cur_sp, NEW_TIMEOUT);
7830 			fas_decrement_ncmds(fas, cur_sp);
7831 			fas_call_pkt_comp(fas, cur_sp);
7838 		fas_remove_cmd(fas, sp, NEW_TIMEOUT);
7839 		fas_decrement_ncmds(fas, sp);
7840 		fas_call_pkt_comp(fas, sp);
7849 		fas_mark_packets(fas, slot, CMD_ABORTED, STAT_ABORTED);
7850 		fas_flush_tagQ(fas, slot);
7851 		fas_flush_readyQ(fas, slot);
7853 	fas_set_throttles(fas, slot, 1, MAX_THROTTLE);
7856 	if (fas->f_state == STATE_FREE) {
7857 		(void) fas_ustart(fas);
7860 	ASSERT(mutex_owned(FAS_MUTEX(fas)));
7874 fas_mark_packets(struct fas *fas, int slot, uchar_t reason, uint_t stat)
7876 	struct fas_cmd *sp = fas->f_readyf[slot];
7879 		fas_set_pkt_reason(fas, sp, reason, STAT_ABORTED);
7882 	if (fas->f_tcmds[slot]) {
7886 		for (tag = 0; tag < fas->f_active[slot]->f_n_slots; tag++) {
7887 			if ((sp = fas->f_active[slot]->f_slot[tag]) != 0) {
7888 				fas_set_pkt_reason(fas, sp, reason, stat);
7892 		ASSERT(fas->f_tcmds[slot] == n);
7900 fas_set_pkt_reason(struct fas *fas, struct fas_cmd *sp, uchar_t reason,
7917 fas_remove_from_readyQ(struct fas *fas, struct fas_cmd *sp, int slot)
7925 		ASSERT(fas->f_ncmds > 0);
7929 		for (psp = NULL, ssp = fas->f_readyf[slot]; ssp != NULL;
7932 				if (fas->f_readyf[slot] == sp) {
7933 					fas->f_readyf[slot] = sp->cmd_forw;
7937 				if (fas->f_readyb[slot] == sp) {
7938 					fas->f_readyb[slot] = psp;
7953 fas_head_of_readyQ(struct fas *fas, struct fas_cmd *sp)
7963 		dp = fas->f_readyf[slot];
7964 		fas->f_readyf[slot] = sp;
7966 		if (fas->f_readyb[slot] == NULL) {
7967 			fas->f_readyb[slot] = sp;
7976 fas_flush_readyQ(struct fas *fas, int slot)
7978 	if (fas->f_readyf[slot]) {
7982 		ASSERT(fas->f_ncmds > 0);
7984 		sp = fas->f_readyf[slot];
7985 		fas->f_readyf[slot] = fas->f_readyb[slot] = NULL;
7995 			fas_decrement_ncmds(fas, sp);
7996 			fas_call_pkt_comp(fas, sp);
7999 		fas_check_ncmds(fas);
8008 fas_flush_tagQ(struct fas *fas, int slot)
8012 	struct f_slots *tagque = fas->f_active[slot];
8019 	    slot, fas->f_tcmds[slot]);
8024 		for (tag = 0; tag < fas->f_active[slot]->f_n_slots; tag++) {
8036 		ASSERT(fas->f_tcmds[slot] == n);
8039 	tag = starttag = fas->f_active[slot]->f_tags;
8043 			fas_flush_cmd(fas, sp, 0, 0);
8046 		    (ushort_t)fas->f_active[slot]->f_n_slots;
8049 	ASSERT(fas->f_tcmds[slot] == 0);
8050 	EPRINTF2("ncmds = %x, ndisc=%x\n", fas->f_ncmds, fas->f_ndisc);
8051 	fas_check_ncmds(fas);
8058 fas_flush_cmd(struct fas *fas, struct fas_cmd *sp, uchar_t reason,
8063 	ASSERT(fas->f_ncmds > 0);
8065 	ASSERT(sp == fas->f_active[slot]->f_slot[sp->cmd_tag[1]]);
8067 	fas_remove_cmd(fas, sp, NEW_TIMEOUT);
8068 	fas_decrement_ncmds(fas, sp);
8069 	fas_set_pkt_reason(fas, sp, reason, stat);
8070 	fas_call_pkt_comp(fas, sp);
8072 	EPRINTF2("ncmds = %x, ndisc=%x\n", fas->f_ncmds, fas->f_ndisc);
8073 	fas_check_ncmds(fas);
8115 fas_do_proxy_cmd(struct fas *fas, struct fas_cmd *sp,
8122 	if (fas_accept_pkt(fas, sp, TRAN_BUSY_OK) == TRAN_ACCEPT &&
8127 		ASSERT(fas->f_current_sp != sp);
8134 		ASSERT(fas->f_current_sp != sp);
8145 fas_abort_connected_cmd(struct fas *fas, struct fas_cmd *sp, uchar_t msg)
8153 	if (fas->f_reset_delay[Tgt(sp)]) {
8160 	if (!((fas->f_state == ACTS_DATA) ||
8161 	    (fas->f_state == ACTS_DATA_DONE))) {
8170 	fas->f_abort_msg_sent = 0;
8171 	fas->f_omsglen = 1;
8172 	fas->f_cur_msgout[0] = msg;
8174 	fas_assert_atn(fas);
8176 	(void) fas_dopoll(fas, SHORT_POLL_TIMEOUT);
8183 	if (fas->f_abort_msg_sent && (sp->cmd_flags & CFLAG_COMPLETED)) {
8192 	fas->f_omsglen = 0;
8201 fas_abort_disconnected_cmd(struct fas *fas, struct scsi_address *ap,
8214 	if (fas->f_reset_delay[target] != 0) {
8226 		ASSERT(sp == fas->f_active[slot]->f_slot[tag]);
8233 	rval = fas_do_proxy_cmd(fas, proxy_cmdp, ap, scsi_mname(msg));
8246 	struct fas *fas = ADDR2FAS(ap);
8249 	ASSERT(mutex_owned(FAS_MUTEX(fas)));
8251 	    slot, level, fas->f_tcmds[slot]);
8253 	fas_move_waitQ_to_readyQ(fas);
8259 		(void) fas_reset_bus(fas);
8266 		if (fas_dopoll(fas, SHORT_POLL_TIMEOUT) <= 0) {
8268 			 * reset fas
8270 			fas_internal_reset(fas, FAS_RESET_FAS);
8271 			(void) fas_reset_bus(fas);
8272 			if (fas_dopoll(fas, SHORT_POLL_TIMEOUT) <= 0) {
8273 				fas_log(fas,
8275 				New_state(fas, STATE_FREE);
8284 		struct fas_cmd *cur_sp = fas->f_current_sp;
8290 		fas_set_all_lun_throttles(fas, slot, HOLD_THROTTLE);
8304 		if (cur_sp && (fas->f_state != STATE_FREE) &&
8307 			rval = fas_reset_connected_cmd(fas, ap);
8315 			rval = fas_reset_disconnected_cmd(fas, ap);
8326 					fas_set_pkt_reason(fas, cur_sp,
8329 				fas_remove_cmd(fas, cur_sp, NEW_TIMEOUT);
8331 				fas_decrement_ncmds(fas, cur_sp);
8332 				fas_call_pkt_comp(fas, cur_sp);
8337 			fas_reset_cleanup(fas, slot);
8348 			fas_set_all_lun_throttles(fas, slot, MAX_THROTTLE);
8352 		if (fas->f_state == STATE_FREE) {
8353 			(void) fas_ustart(fas);
8357 	ASSERT(mutex_owned(FAS_MUTEX(fas)));
8358 	ASSERT(fas->f_ncmds >= fas->f_ndisc);
8373 fas_start_watch_reset_delay(struct fas *fas)
8380 	ASSERT((fas_reset_watch != 0) || (fas->f_flags & FAS_FLG_NOTIMEOUTS));
8388 fas_setup_reset_delay(struct fas *fas)
8393 		fas_set_throttles(fas, 0, N_SLOTS, HOLD_THROTTLE);
8395 			fas->f_reset_delay[i] = fas->f_scsi_reset_delay;
8397 		fas_start_watch_reset_delay(fas);
8399 		drv_usecwait(fas->f_scsi_reset_delay * 1000);
8405  * fas instance for active reset delays
8411 	struct fas *fas;
8412 	struct fas *lfas;	/* last not_done fas */
8420 	for (fas = fas_head; fas != (struct fas *)NULL; fas = fas->f_next) {
8421 		if (fas->f_tran == 0) {
8424 		mutex_enter(FAS_MUTEX(fas));
8425 		not_done += fas_watch_reset_delay_subr(fas);
8426 		lfas = fas;
8427 		fas_check_waitQ_and_mutex_exit(fas);
8437 fas_watch_reset_delay_subr(struct fas *fas)
8450 		if (fas->f_reset_delay[s] != 0) {
8452 			    fas->f_reset_delay[s]);
8453 			fas->f_reset_delay[s] -= FAS_WATCH_RESET_DELAY_TICK;
8454 			if (fas->f_reset_delay[s] <= 0) {
8458 				fas->f_reset_delay[s] = 0;
8459 				fas_set_all_lun_throttles(fas,
8475 	if (start_slot != -1 && fas->f_state == STATE_FREE) {
8476 		(void) fas_ustart(fas);
8485 fas_reset_cleanup(struct fas *fas, int slot)
8497 	    slot, start, end, fas->f_tcmds[slot]);
8499 	ASSERT(!(fas->f_current_sp &&
8500 	    (fas->f_current_sp->cmd_slot == slot) &&
8501 	    (fas->f_state & STATE_SELECTING)));
8508 		fas_set_all_lun_throttles(fas, start, HOLD_THROTTLE);
8509 		fas->f_reset_delay[target] = fas->f_scsi_reset_delay;
8510 		fas_start_watch_reset_delay(fas);
8512 		drv_usecwait(fas->f_scsi_reset_delay * 1000);
8516 		fas_mark_packets(fas, i, CMD_RESET, STAT_DEV_RESET);
8517 		fas_flush_tagQ(fas, i);
8518 		fas_flush_readyQ(fas, i);
8519 		if (fas->f_arq_pkt[i]) {
8520 			struct fas_cmd *sp = fas->f_arq_pkt[i];
8528 		ASSERT(fas->f_tcmds[i] == 0);
8530 	ASSERT(fas->f_ncmds >= fas->f_ndisc);
8532 	fas_force_renegotiation(fas, target);
8539 fas_reset_disconnected_cmd(struct fas *fas, struct scsi_address *ap)
8548 	rval = fas_do_proxy_cmd(fas, sp, ap, scsi_mname(MSG_DEVICE_RESET));
8559 fas_reset_connected_cmd(struct fas *fas, struct scsi_address *ap)
8562 	struct fas_cmd *sp = fas->f_current_sp;
8569 	if (!((fas->f_state == ACTS_DATA) ||
8570 	    (fas->f_state == ACTS_DATA_DONE))) {
8576 	fas->f_reset_msg_sent = 0;
8577 	fas->f_omsglen = 1;
8578 	fas->f_cur_msgout[0] = MSG_DEVICE_RESET;
8581 	fas_assert_atn(fas);
8586 	(void) fas_dopoll(fas, SHORT_POLL_TIMEOUT);
8593 	if (fas->f_reset_msg_sent && (sp->cmd_flags & CFLAG_COMPLETED)) {
8601 	fas->f_omsglen = 0;
8610 fas_reset_bus(struct fas *fas)
8613 	New_state(fas, ACTS_RESET);
8615 	fas_internal_reset(fas, FAS_RESET_SCSIBUS);
8629 fas_reset_recovery(struct fas *fas)
8637 	fas_check_ncmds(fas);
8642 	fas->f_sync_known = fas->f_wide_known = 0;
8647 	FAS_FLUSH_DMA_HARD(fas);
8652 	fas_setup_reset_delay(fas);
8657 	while (INTPENDING(fas) && (max_loop < FAS_RESET_SPIN_MAX_LOOP)) {
8658 		volatile struct fasreg *fasreg = fas->f_reg;
8659 		fas->f_stat = fas_reg_read(fas, &fasreg->fas_stat);
8660 		fas->f_stat2 = fas_reg_read(fas, &fasreg->fas_stat2);
8661 		fas->f_step = fas_reg_read(fas, &fasreg->fas_step);
8662 		fas->f_intr = fas_reg_read(fas, &fasreg->fas_intr);
8668 		fas_log(fas, CE_WARN, "Resetting SCSI bus failed");
8671 	fas_reg_cmd_write(fas, CMD_FLUSH);
8677 	fas_internal_reset(fas, FAS_RESET_FAS);
8682 	if (fas->f_state != ACTS_RESET) {
8683 		if (fas->f_ncmds) {
8684 			fas_log(fas, CE_WARN, "external SCSI bus reset");
8688 	if (fas->f_ncmds == 0) {
8696 	fas_internal_reset(fas, FAS_RESET_SOFTC);
8701 	New_state(fas, ACTS_FROZEN);
8709 	start_slot = fas->f_next_slot;
8712 		fas_check_ncmds(fas);
8713 		fas_mark_packets(fas, slot, CMD_RESET, STAT_BUS_RESET);
8714 		fas_flush_tagQ(fas, slot);
8715 		fas_flush_readyQ(fas, slot);
8716 		if (fas->f_arq_pkt[slot]) {
8717 			struct fas_cmd *sp = fas->f_arq_pkt[slot];
8725 		slot = NEXTSLOT(slot, fas->f_dslot);
8728 	fas_check_ncmds(fas);
8734 		if (fas->f_active[i]) {
8735 			fas->f_active[i]->f_timebase = 0;
8736 			fas->f_active[i]->f_timeout = 0;
8737 			fas->f_active[i]->f_dups = 0;
8745 	New_state(fas, STATE_FREE);
8746 	ASSERT(fas->f_ncmds >= fas->f_ndisc);
8751 	(void) scsi_hba_reset_notify_callback(&fas->f_mutex,
8752 	    &fas->f_reset_notify_listf);
8767 	struct fas *fas;
8771 	if ((tran == NULL) || ((fas = TRAN2FAS(tran)) == NULL)) {
8775 	return (fas_quiesce_bus(fas));
8781 	struct fas *fas;
8785 	if ((tran == NULL) || ((fas = TRAN2FAS(tran)) == NULL)) {
8789 	return (fas_unquiesce_bus(fas));
8797 fas_test_reset(struct fas *fas, int slot)
8803 		ap.a_hba_tran = fas->f_tran;
8807 		    (fas->f_state == ACTS_DATA_DONE)) {
8812 		    (fas->f_state == ACTS_DATA_DONE)) {
8825 fas_test_abort(struct fas *fas, int slot)
8827 	struct fas_cmd *sp = fas->f_current_sp;
8833 		ap.a_hba_tran = fas->f_tran;
8842 			sp = fas->f_active[slot]->f_slot[0];
8848 		    (fas->f_tcmds[slot] != 0)) {
8854 				if ((sp = fas->f_active[slot]->f_slot[tag])
8865 		    (fas->f_tcmds[slot] != 0)) {
8869 		} else if (fas_atest_disc == 3 && fas->f_readyf[slot]) {
8870 			pkt = fas->f_readyf[slot]->cmd_pkt;
8872 		    fas->f_readyf[slot] && fas->f_readyf[slot]->cmd_forw) {
8873 			pkt = fas->f_readyf[slot]->cmd_forw->cmd_pkt;
8874 		} else if (fas_atest_disc == 5 && fas->f_readyb[slot]) {
8875 			pkt = fas->f_readyb[slot]->cmd_pkt;
8878 		    (fas->f_state == ACTS_DATA_DONE)) {
8894 		fas_log(fas, CE_NOTE, "aborting pkt=0x%p state=%x\n",
8910 	struct fas *fas = ADDR2FAS(ap);
8917 	mutex_enter(FAS_MUTEX(fas));
8950 				fas->f_target_scsi_options[ap->a_target] |=
8953 				fas->f_target_scsi_options[ap->a_target] &=
8960 				fas->f_force_async &= ~tshift;
8962 				fas->f_force_async |= tshift;
8964 			fas_force_renegotiation(fas, target);
8971 			ushort_t old_notag = fas->f_notag;
8974 			if (fas->f_tcmds[slot]) {
8981 				if (fas->f_target_scsi_options[target] &
8985 					fas->f_notag &= ntshift;
8992 				fas->f_notag |= tshift;
8995 			if (val && fas_alloc_active_slots(fas, slot,
8997 				fas->f_notag = old_notag;
9001 			fas_set_all_lun_throttles(fas, slot, MAX_THROTTLE);
9003 			fas_update_props(fas, target);
9010 				if (fas->f_target_scsi_options[target] &
9012 					fas->f_nowide &= ntshift;
9013 					fas->f_force_narrow &= ~tshift;
9018 				fas->f_force_narrow |= tshift;
9020 			fas_force_renegotiation(fas, target);
9026 				if (fas_create_arq_pkt(fas, ap)) {
9030 				if (fas_delete_arq_pkt(fas, ap)) {
9038 			fas->f_qfull_retries[target] = (uchar_t)val;
9043 			fas->f_qfull_retry_interval[target] =
9066 			    (fas->f_target_scsi_options[target] &
9072 			if (tgtonly && fas->f_offset[target]) {
9080 			rval = MY_ID(fas);
9083 			if (tgtonly && ((fas->f_notag & tshift) == 0)) {
9088 			if ((tgtonly && (fas->f_nowide & tshift) == 0)) {
9096 			if (tgtonly && fas->f_arq_pkt[slot]) {
9106 			rval = fas->f_qfull_retries[target];
9110 			    fas->f_qfull_retry_interval[target]) /
9121 		fas_update_props(fas, target);
9123 	fas_check_waitQ_and_mutex_exit(fas);
9139 fas_update_props(struct fas *fas, int tgt)
9145 	uint_t	regval = fas->f_sync_period[tgt];
9146 	int	offset = fas->f_offset[tgt];
9148 	wide_enabled = ((fas->f_nowide & (1<<tgt)) == 0);
9151 		    FAS_SYNC_KBPS((regval * fas->f_clock_cycle) / 1000);
9155 	fas_update_this_prop(fas, property, xfer_rate);
9158 	fas_update_this_prop(fas, property, wide_enabled);
9161 	tq_enabled = ((fas->f_notag & (1<<tgt))? 0 : 1);
9162 	fas_update_this_prop(fas, property, tq_enabled);
9167 fas_update_this_prop(struct fas *fas, char *property, int value)
9169 	dev_info_t *dip = fas->f_dev;
9172 	ASSERT(mutex_owned(FAS_MUTEX(fas)));
9177 	mutex_exit(FAS_MUTEX(fas));
9182 	mutex_enter(FAS_MUTEX(fas));
9189 fas_alloc_active_slots(struct fas *fas, int slot, int flag)
9192 	struct f_slots *old_active = fas->f_active[slot];
9197 	if (fas->f_tcmds[slot]) {
9212 		fas->f_active[slot] = new_active;
9213 		fas->f_active[slot]->f_n_slots = (NOTAG(target) ? 1 : NTAGS);
9214 		fas->f_active[slot]->f_size = size;
9219 			fas->f_active[slot]->f_tags = 1;
9232 static char *fas_label = "fas";
9236 fas_log(struct fas *fas, int level, const char *fmt, ...)
9241 	if (fas) {
9242 		dev = fas->f_dev;
9264 fas_printf(struct fas *fas, const char *fmt, ...)
9276 	if (fas) {
9277 		dev = fas->f_dev;
9290 fas_dprintf(struct fas *fas, const char *fmt, ...)
9295 	if (fas) {
9296 		dev = fas->f_dev;
9313 fas_printstate(struct fas *fas, char *msg)
9315 	volatile struct fasreg *fasreg = fas->f_reg;
9316 	volatile struct dma *dmar = fas->f_dma;
9317 	uint_t csr = fas_dma_reg_read(fas, &dmar->dma_csr);
9318 	uint_t count = fas_dma_reg_read(fas, &dmar->dma_count);
9319 	uint_t addr = fas_dma_reg_read(fas, &dmar->dma_addr);
9320 	uint_t test = fas_dma_reg_read(fas, &dmar->dma_test);
9323 	fas_log(fas, CE_WARN, "%s: current fas state:", msg);
9325 	    fas->f_stat, FAS_STAT_BITS, fas->f_intr, FAS_INT_BITS);
9327 	    scsi_mname(fas->f_last_msgout), scsi_mname(fas->f_last_msgin));
9331 	    addr, count, test, fas->f_lastdma, fas->f_lastcount);
9334 	fas_printf(NULL, "fas state:");
9343 	if (fas->f_current_sp) {
9344 		fas_dump_cmd(fas, fas->f_current_sp);
9352 fas_dump_cmd(struct fas *fas, struct fas_cmd *sp)
9368 	    fas_state_name(fas->f_state), fas_state_name(fas->f_laststate));
9380 fas_short_dump_cmd(struct fas *fas, struct fas_cmd *sp)