Lines Matching refs:state
421 CS_state_t *state;
426 /* get the state structure */
427 state = ddi_get_driver_private(dip);
429 ASSERT(!mutex_owned(&state->cs_lock));
432 mutex_enter(&state->cs_lock);
438 if (!state->cs_suspended) {
441 if (level == CS4231_PWR_OFF && state->cs_powered) {
443 /* power down and save the state */
444 audiocs_power_down(state);
445 state->cs_powered = B_FALSE;
447 } else if (level == CS4231_PWR_ON && !state->cs_powered) {
450 audiocs_power_up(state);
451 state->cs_powered = B_TRUE;
455 mutex_exit(&state->cs_lock);
457 ASSERT(!mutex_owned(&state->cs_lock));
465 audiocs_destroy(CS_state_t *state)
467 if (state == NULL)
471 audiocs_free_engine(state->cs_engines[i]);
473 audiocs_del_controls(state);
475 if (state->cs_adev) {
476 audio_dev_free(state->cs_adev);
480 CS4231_DMA_UNMAP_REGS(state);
482 /* destroy the state mutex */
483 mutex_destroy(&state->cs_lock);
484 kmem_free(state, sizeof (*state));
505 CS_state_t *state;
508 /* allocate the state structure */
509 state = kmem_zalloc(sizeof (*state), KM_SLEEP);
510 state->cs_dip = dip;
511 ddi_set_driver_private(dip, state);
513 /* now fill it in, initialize the state mutexs first */
514 mutex_init(&state->cs_lock, NULL, MUTEX_DRIVER, NULL);
517 * audio state initialization... should always succeed,
520 if ((state->cs_adev = audio_dev_alloc(dip, 0)) == NULL) {
523 adev = state->cs_adev;
527 /* initialize the audio state structures */
528 if ((audiocs_init_state(state)) == DDI_FAILURE) {
533 mutex_enter(&state->cs_lock);
536 if ((audiocs_chip_init(state)) == DDI_FAILURE) {
537 mutex_exit(&state->cs_lock);
542 state->cs_powered = B_TRUE;
544 mutex_exit(&state->cs_lock);
547 if (audio_dev_register(state->cs_adev) != DDI_SUCCESS) {
548 audio_dev_warn(state->cs_adev, "unable to register audio dev");
557 audiocs_destroy(state);
577 CS_state_t *state;
580 /* we've already allocated the state structure so get ptr */
581 state = ddi_get_driver_private(dip);
582 adev = state->cs_adev;
584 ASSERT(dip == state->cs_dip);
585 ASSERT(!mutex_owned(&state->cs_lock));
588 (void) pm_busy_component(state->cs_dip, CS4231_COMPONENT);
591 audiocs_power_up(state);
592 state->cs_powered = B_TRUE;
594 mutex_enter(&state->cs_lock);
597 if ((audiocs_chip_init(state)) == DDI_FAILURE) {
598 mutex_exit(&state->cs_lock);
600 (void) pm_idle_component(state->cs_dip, CS4231_COMPONENT);
604 state->cs_suspended = B_FALSE;
606 mutex_exit(&state->cs_lock);
613 (void) pm_idle_component(state->cs_dip, CS4231_COMPONENT);
615 audio_dev_resume(state->cs_adev);
636 CS_state_t *state;
640 /* get the state structure */
641 state = ddi_get_driver_private(dip);
643 adev = state->cs_adev;
650 if (state->cs_powered) {
654 SELIDX(state, INTC_REG);
655 ANDIDX(state, ~(INTC_PEN|INTC_CEN), INTC_VALID_MASK);
658 CS4231_DMA_RESET(state);
667 audiocs_destroy(state);
688 CS_state_t *state;
690 /* get the state structure */
691 state = ddi_get_driver_private(dip);
693 mutex_enter(&state->cs_lock);
695 ASSERT(!state->cs_suspended);
697 audio_dev_suspend(state->cs_adev);
699 if (state->cs_powered) {
701 audiocs_power_down(state);
702 state->cs_powered = B_FALSE;
704 state->cs_suspended = B_TRUE; /* stop new ops */
705 mutex_exit(&state->cs_lock);
725 * CS_state_t *state Device soft state.
733 audiocs_alloc_ctrl(CS_state_t *state, uint32_t num, uint64_t val)
740 cc->cc_state = state;
776 desc.acd_minvalue = state->cs_imask;
777 desc.acd_maxvalue = state->cs_imask;
789 desc.acd_minvalue = state->cs_omod;
790 desc.acd_maxvalue = state->cs_omask;
809 cc->cc_ctrl = audio_dev_add_control(state->cs_adev, &desc,
841 * CS_state_t *state Device soft state.
848 audiocs_add_controls(CS_state_t *state)
851 state->cs_##CTL = audiocs_alloc_ctrl(state, ID, VAL); \
852 if (state->cs_##CTL == NULL) { \
853 audio_dev_warn(state->cs_adev, \
862 ADD_CTRL(outputs, CTL_OUTPUTS, (state->cs_omask & ~state->cs_omod) |
876 * CS_state_t *state Device soft state.
879 audiocs_del_controls(CS_state_t *state)
881 audiocs_free_ctrl(state->cs_ogain);
882 audiocs_free_ctrl(state->cs_igain);
883 audiocs_free_ctrl(state->cs_mgain);
884 audiocs_free_ctrl(state->cs_micboost);
885 audiocs_free_ctrl(state->cs_inputs);
886 audiocs_free_ctrl(state->cs_outputs);
898 * CS_state_t *state The device's state structure
905 audiocs_chip_init(CS_state_t *state)
910 CS4231_DMA_POWER(state, CS4231_PWR_ON);
912 CS4231_DMA_RESET(state);
915 if (audiocs_poll_ready(state) == DDI_FAILURE) {
920 SELIDX(state, MID_REG);
924 SELIDX(state, VID_REG);
926 state->cs_revA = B_TRUE;
928 state->cs_revA = B_FALSE;
932 SELIDX(state, LDACO_REG);
933 PUTIDX(state, LDACO_LDM | LDACO_MID_GAIN, LDAC0_VALID_MASK);
934 SELIDX(state, RDACO_REG);
935 PUTIDX(state, RDACO_RDM | RDACO_MID_GAIN, RDAC0_VALID_MASK);
938 SELIDX(state, LAUX1_REG);
939 PUTIDX(state, LAUX1_LX1M | LAUX1_UNITY_GAIN, LAUX1_VALID_MASK);
940 SELIDX(state, RAUX1_REG);
941 PUTIDX(state, RAUX1_RX1M | RAUX1_UNITY_GAIN, RAUX1_VALID_MASK);
942 SELIDX(state, LAUX2_REG);
943 PUTIDX(state, LAUX2_LX2M | LAUX2_UNITY_GAIN, LAUX2_VALID_MASK);
944 SELIDX(state, RAUX2_REG);
945 PUTIDX(state, RAUX2_RX2M | RAUX2_UNITY_GAIN, RAUX2_VALID_MASK);
948 SELIDX(state, LLIC_REG);
949 PUTIDX(state, LLIC_LLM | LLIC_UNITY_GAIN, LLIC_VALID_MASK);
950 SELIDX(state, RLIC_REG);
951 PUTIDX(state, RLIC_RLM | RLIC_UNITY_GAIN, RLIC_VALID_MASK);
954 SELIDX(state, FSDF_REG | IAR_MCE);
955 PUTIDX(state, FS_48000 | PDF_LINEAR16NE | PDF_STEREO, FSDF_VALID_MASK);
956 if (audiocs_poll_ready(state) == DDI_FAILURE) {
960 SELIDX(state, CDF_REG | IAR_MCE);
961 PUTIDX(state, CDF_LINEAR16NE | CDF_STEREO, CDF_VALID_MASK);
962 if (audiocs_poll_ready(state) == DDI_FAILURE) {
970 SELIDX(state, (INTC_REG | IAR_MCE));
971 PUTIDX(state, INTC_DDC | INTC_PDMA | INTC_CDMA, INTC_VALID_MASK);
972 if (audiocs_poll_ready(state) == DDI_FAILURE) {
980 SELIDX(state, AFE1_REG);
981 PUTIDX(state, AFE1_OLB, AFE1_VALID_MASK);
984 SELIDX(state, AFE2_REG);
985 if (state->cs_revA) {
986 PUTIDX(state, AFE2_HPF, AFE2_VALID_MASK);
988 PUTIDX(state, 0, AFE2_VALID_MASK);
993 SELIDX(state, AFS_REG);
999 SELIDX(state, LDACO_REG);
1000 ANDIDX(state, ~LDACO_LDM, LDAC0_VALID_MASK);
1001 SELIDX(state, RDACO_REG);
1002 ANDIDX(state, ~RDACO_RDM, RDAC0_VALID_MASK);
1005 SELIDX(state, MIOC_REG);
1006 PUTIDX(state, MIOC_MIM, MIOC_VALID_MASK);
1008 audiocs_configure_output(state);
1009 audiocs_configure_input(state);
1018 * This routine initializes the audio driver's state structure and
1026 * CS_state_t *state The device's state structure
1033 audiocs_init_state(CS_state_t *state)
1035 audio_dev_t *adev = state->cs_adev;
1036 dev_info_t *dip = state->cs_dip;
1054 state->cs_dma_engine = EB2_DMA;
1055 state->cs_dma_ops = &cs4231_eb2dma_ops;
1057 state->cs_dma_engine = APC_DMA;
1058 state->cs_dma_ops = &cs4231_apcdma_ops;
1062 state->cs_dma_engine = APC_DMA;
1063 state->cs_dma_ops = &cs4231_apcdma_ops;
1070 audiocs_get_ports(state);
1073 if ((audiocs_alloc_engine(state, CS4231_PLAY) != DDI_SUCCESS) ||
1074 (audiocs_alloc_engine(state, CS4231_REC) != DDI_SUCCESS)) {
1079 if (CS4231_DMA_MAP_REGS(state) == DDI_FAILURE) {
1085 if (audiocs_add_controls(state) != DDI_SUCCESS) {
1089 state->cs_suspended = B_FALSE;
1090 state->cs_powered = B_FALSE;
1142 * CS_state_t *state The device's state structure
1145 audiocs_get_ports(CS_state_t *state)
1147 dev_info_t *dip = state->cs_dip;
1148 audio_dev_t *adev = state->cs_adev;
1152 state->cs_omask = state->cs_omod =
1156 state->cs_imask =
1167 state->cs_imask |= (1U << INPUT_CD);
1168 state->cs_omod = (1U << OUTPUT_SPEAKER);
1211 if (state->cs_dma_engine == EB2_DMA) {
1224 state->cs_imask |= (1U << INPUT_CD);
1241 * CS_state_t *state The device's state structure
1244 audiocs_power_up(CS_state_t *state)
1250 CS4231_DMA_POWER(state, CS4231_PWR_ON);
1253 CS4231_DMA_RESET(state);
1255 (void) audiocs_poll_ready(state);
1262 SELIDX(state, MID_REG);
1263 PUTIDX(state, state->cs_save[MID_REG], MID_VALID_MASK);
1267 SELIDX(state, (i | IAR_MCE));
1268 ddi_put8(handle, &CS4231_IDR, state->cs_save[i]);
1269 (void) audiocs_poll_ready(state);
1272 SELIDX(state, 0);
1284 * CS_state_t *state The device's state structure
1287 audiocs_power_down(CS_state_t *state)
1292 handle = state->cs_handles.cs_codec_hndl;
1302 SELIDX(state, i);
1303 state->cs_save[i] = ddi_get8(handle, &CS4231_IDR);
1307 CS4231_DMA_POWER(state, CS4231_PWR_OFF);
1318 * CS_state_t *state The device's state structure
1321 audiocs_configure_input(CS_state_t *state)
1327 ASSERT(mutex_owned(&state->cs_lock));
1329 inputs = state->cs_inputs->cc_val;
1330 micboost = state->cs_micboost->cc_val;
1331 r = (state->cs_igain->cc_val & 0xff);
1332 l = ((state->cs_igain->cc_val & 0xff00) >> 8);
1365 SELIDX(state, LADCI_REG);
1366 PUTIDX(state, l, LADCI_VALID_MASK);
1368 SELIDX(state, RADCI_REG);
1369 PUTIDX(state, r, RADCI_VALID_MASK);
1379 * CS_state_t *state The device's state structure
1382 audiocs_configure_output(CS_state_t *state)
1392 ASSERT(mutex_owned(&state->cs_lock));
1394 outputs = state->cs_outputs->cc_val;
1397 SELIDX(state, MIOC_REG);
1399 ANDIDX(state, ~MIOC_MONO_SPKR_MUTE, MIOC_VALID_MASK);
1401 ORIDX(state, MIOC_MONO_SPKR_MUTE, MIOC_VALID_MASK);
1403 SELIDX(state, PC_REG);
1405 ANDIDX(state, ~PC_HEADPHONE_MUTE, PC_VALID_MASK);
1407 ORIDX(state, PC_HEADPHONE_MUTE, PC_VALID_MASK);
1409 SELIDX(state, PC_REG);
1411 ANDIDX(state, ~PC_LINE_OUT_MUTE, PC_VALID_MASK);
1413 ORIDX(state, PC_LINE_OUT_MUTE, PC_VALID_MASK);
1417 mgain = cs4231_atten[((state->cs_mgain->cc_val * 255) / 100) & 0xff];
1418 SELIDX(state, LC_REG);
1421 PUTIDX(state, LC_OFF, LC_VALID_MASK);
1424 PUTIDX(state, (mgain << 2) | LC_LBE, LC_VALID_MASK);
1428 l = ((state->cs_ogain->cc_val >> 8) & 0xff);
1429 r = (state->cs_ogain->cc_val & 0xff);
1441 SELIDX(state, LDACO_REG);
1442 PUTIDX(state, l, LDAC0_VALID_MASK);
1443 SELIDX(state, RDACO_REG);
1444 PUTIDX(state, r, RDAC0_VALID_MASK);
1454 * void *arg The device's state structure
1464 CS_state_t *state = cc->cc_state;
1466 mutex_enter(&state->cs_lock);
1468 mutex_exit(&state->cs_lock);
1480 * void *arg The device's state structure
1490 CS_state_t *state = cc->cc_state;
1497 mutex_enter(&state->cs_lock);
1499 audiocs_configure_output(state);
1500 mutex_exit(&state->cs_lock);
1511 * void *arg The device's state structure
1521 CS_state_t *state = cc->cc_state;
1523 mutex_enter(&state->cs_lock);
1525 audiocs_configure_input(state);
1526 mutex_exit(&state->cs_lock);
1537 * void *arg The device's state structure
1547 CS_state_t *state = cc->cc_state;
1554 mutex_enter(&state->cs_lock);
1556 audiocs_configure_input(state);
1557 mutex_exit(&state->cs_lock);
1569 * void *arg The device's state structure
1579 CS_state_t *state = cc->cc_state;
1581 if (val & ~(state->cs_imask))
1584 mutex_enter(&state->cs_lock);
1586 audiocs_configure_input(state);
1587 mutex_exit(&state->cs_lock);
1599 * void *arg The device's state structure
1609 CS_state_t *state = cc->cc_state;
1611 if ((val & ~(state->cs_omod)) !=
1612 (state->cs_omask & ~state->cs_omod))
1615 mutex_enter(&state->cs_lock);
1617 audiocs_configure_output(state);
1618 mutex_exit(&state->cs_lock);
1630 * void *arg The device's state structure
1640 CS_state_t *state = cc->cc_state;
1645 mutex_enter(&state->cs_lock);
1647 audiocs_configure_output(state);
1648 mutex_exit(&state->cs_lock);
1673 CS_state_t *state = eng->ce_state;
1674 dev_info_t *dip = state->cs_dip;
1685 audio_dev_warn(state->cs_adev, "power up failed");
1710 CS_state_t *state = eng->ce_state;
1712 (void) pm_idle_component(state->cs_dip, CS4231_COMPONENT);
1729 CS_state_t *state = eng->ce_state;
1732 mutex_enter(&state->cs_lock);
1736 CS4231_DMA_STOP(state, eng);
1741 SELIDX(state, INTC_REG);
1742 ANDIDX(state, ~(eng->ce_codec_en), INTC_VALID_MASK);
1743 mutex_exit(&state->cs_lock);
1762 CS_state_t *state = eng->ce_state;
1769 mutex_enter(&state->cs_lock);
1784 SELIDX(state, reg | IAR_MCE);
1785 PUTIDX(state, value, mask);
1787 if (audiocs_poll_ready(state) != DDI_SUCCESS) {
1789 } else if (CS4231_DMA_START(state, eng) != DDI_SUCCESS) {
1795 SELIDX(state, INTC_REG);
1796 ORIDX(state, eng->ce_codec_en, INTC_VALID_MASK);
1800 mutex_exit(&state->cs_lock);
1880 CS_state_t *state = eng->ce_state;
1884 mutex_enter(&state->cs_lock);
1886 off = CS4231_DMA_ADDR(state, eng);
1912 CS4231_DMA_RELOAD(state, eng);
1913 mutex_exit(&state->cs_lock);
1943 * CS_state_t *dip Pointer to the device's soft state
1951 audiocs_alloc_engine(CS_state_t *state, int num)
1969 adev = state->cs_adev;
1970 dip = state->cs_dip;
1973 eng->ce_state = state;
1995 state->cs_engines[num] = eng;
1998 rc = ddi_dma_alloc_handle(dip, CS4231_DMA_ATTR(state), DDI_DMA_SLEEP,
2048 CS_state_t *state = eng->ce_state;
2049 audio_dev_t *adev = state->cs_adev;
2081 * CS_state_t *state The device's state structure
2088 audiocs_poll_ready(CS_state_t *state)
2095 ASSERT(state->cs_regs != NULL);
2116 SELIDX(state, ESI_REG);
2151 audiocs_sel_index(CS_state_t *state, uint8_t reg, int n)
2153 audiocs_sel_index(CS_state_t *state, uint8_t reg)
2171 audio_dev_warn(state->cs_adev,
2178 audio_dev_warn(state->cs_adev,
2195 * CS_state_t state Handle to this device
2201 audiocs_put_index(CS_state_t *state, uint8_t val, uint8_t mask, int n)
2203 audiocs_put_index(CS_state_t *state, uint8_t val, uint8_t mask)
2224 audio_dev_warn(state->cs_adev,
2227 audio_dev_warn(state->cs_adev,
2230 audio_dev_warn(state->cs_adev,