Lines Matching refs:rp
329 struct regs *rp = lwptoregs(lwp);
340 rp->r_tstate &= ~(((uint64_t)TSTATE_CCR_MASK << TSTATE_CCR_SHIFT) |
342 rp->r_tstate |= tbits;
353 rp->r_pc = grp[REG_PC] & ~03L;
354 rp->r_npc = grp[REG_nPC] & ~03L;
355 rp->r_y = grp[REG_Y];
357 rp->r_g1 = grp[REG_G1];
358 rp->r_g2 = grp[REG_G2];
359 rp->r_g3 = grp[REG_G3];
360 rp->r_g4 = grp[REG_G4];
361 rp->r_g5 = grp[REG_G5];
362 rp->r_g6 = grp[REG_G6];
363 rp->r_g7 = grp[REG_G7];
365 rp->r_o0 = grp[REG_O0];
366 rp->r_o1 = grp[REG_O1];
367 rp->r_o2 = grp[REG_O2];
368 rp->r_o3 = grp[REG_O3];
369 rp->r_o4 = grp[REG_O4];
370 rp->r_o5 = grp[REG_O5];
371 rp->r_o6 = grp[REG_O6];
372 rp->r_o7 = grp[REG_O7];
393 struct regs *rp = lwptoregs(lwp);
404 grp[REG_CCR] = (rp->r_tstate >> TSTATE_CCR_SHIFT) & TSTATE_CCR_MASK;
405 grp[REG_PC] = rp->r_pc;
406 grp[REG_nPC] = rp->r_npc;
407 grp[REG_Y] = (uint32_t)rp->r_y;
408 grp[REG_G1] = rp->r_g1;
409 grp[REG_G2] = rp->r_g2;
410 grp[REG_G3] = rp->r_g3;
411 grp[REG_G4] = rp->r_g4;
412 grp[REG_G5] = rp->r_g5;
413 grp[REG_G6] = rp->r_g6;
414 grp[REG_G7] = rp->r_g7;
415 grp[REG_O0] = rp->r_o0;
416 grp[REG_O1] = rp->r_o1;
417 grp[REG_O2] = rp->r_o2;
418 grp[REG_O3] = rp->r_o3;
419 grp[REG_O4] = rp->r_o4;
420 grp[REG_O5] = rp->r_o5;
421 grp[REG_O6] = rp->r_o6;
422 grp[REG_O7] = rp->r_o7;
423 grp[REG_ASI] = (rp->r_tstate >> TSTATE_ASI_SHIFT) & TSTATE_ASI_MASK;
430 struct regs *rp = lwptoregs(lwp);
441 grp[REG_PSR] = mkpsr(rp->r_tstate, fprs);
442 grp[REG_PC] = rp->r_pc;
443 grp[REG_nPC] = rp->r_npc;
444 grp[REG_Y] = rp->r_y;
445 grp[REG_G1] = rp->r_g1;
446 grp[REG_G2] = rp->r_g2;
447 grp[REG_G3] = rp->r_g3;
448 grp[REG_G4] = rp->r_g4;
449 grp[REG_G5] = rp->r_g5;
450 grp[REG_G6] = rp->r_g6;
451 grp[REG_G7] = rp->r_g7;
452 grp[REG_O0] = rp->r_o0;
453 grp[REG_O1] = rp->r_o1;
454 grp[REG_O2] = rp->r_o2;
455 grp[REG_O3] = rp->r_o3;
456 grp[REG_O4] = rp->r_o4;
457 grp[REG_O5] = rp->r_o5;
458 grp[REG_O6] = rp->r_o6;
459 grp[REG_O7] = rp->r_o7;
795 struct regs *rp;
805 rp = lwptoregs(lwp);
806 rp->r_g1 = rp->r_g2 = rp->r_g3 = rp->r_g4 = rp->r_g5 =
807 rp->r_g6 = rp->r_o0 = rp->r_o1 = rp->r_o2 =
808 rp->r_o3 = rp->r_o4 = rp->r_o5 = rp->r_o7 = 0;
810 rp->r_tstate = TSTATE_USER32 | weakest_mem_model;
812 rp->r_tstate = TSTATE_USER64 | weakest_mem_model;
814 rp->r_tstate &= ~TSTATE_PEF;
815 rp->r_g7 = args->thrptr;
816 rp->r_pc = args->entry;
817 rp->r_npc = args->entry + 4;
818 rp->r_y = 0;
890 struct regs *volatile rp;
921 rp = lwptoregs(lwp);
973 tos = (caddr_t)rp->r_sp + STACK_BIAS;
1013 (void *)fp, (void *)hdlr, rp->r_pc);
1161 rp->r_sp = (uintptr_t)fp - STACK_BIAS;
1162 rp->r_pc = (uintptr_t)hdlr;
1163 rp->r_npc = (uintptr_t)hdlr + 4;
1165 rp->r_tstate &= ~((uint64_t)TSTATE_ASI_MASK << TSTATE_ASI_SHIFT);
1166 rp->r_tstate |= ((uint64_t)ASI_PNF << TSTATE_ASI_SHIFT);
1167 rp->r_o0 = sig;
1168 rp->r_o1 = (uintptr_t)sip_addr;
1169 rp->r_o2 = (uintptr_t)&fp->uc;
1193 (void *)fp, (void *)hdlr, rp->r_pc);
1219 struct regs *volatile rp;
1252 rp = lwptoregs(lwp);
1302 tos = (void *)(uintptr_t)(uint32_t)rp->r_sp;
1343 (void *)fp, (void *)hdlr, rp->r_pc);
1504 rp->r_sp = (uintptr_t)fp;
1505 rp->r_pc = (uintptr_t)hdlr;
1506 rp->r_npc = (uintptr_t)hdlr + 4;
1508 rp->r_tstate &= ~((uint64_t)TSTATE_ASI_MASK << TSTATE_ASI_SHIFT);
1509 rp->r_tstate |= ((uint64_t)ASI_PNF << TSTATE_ASI_SHIFT);
1510 rp->r_o0 = sig;
1511 rp->r_o1 = (uintptr_t)sip_addr;
1512 rp->r_o2 = (uintptr_t)&fp->uc;
1536 (void *)fp, (void *)hdlr, rp->r_pc);
1570 struct regs *rp = lwptoregs(lwp);
1572 rp->r_tstate &= ~TSTATE_IC;
1573 rp->r_o0 = v1;
1574 rp->r_o1 = v2;
1583 struct regs *rp = lwptoregs(lwp);
1584 rp->r_sp = (uintptr_t)sp;
1627 struct regs *rp = lwptoregs(ttolwp(curthread));
1634 rp->r_tstate &= ~TSTATE_MM;
1636 rp->r_tstate |= TSTATE_MM_TSO;
1849 panic_saveregs(panic_data_t *pdp, struct regs *rp)
1853 PANICNVADD(pnv, "tstate", rp->r_tstate);
1854 PANICNVADD(pnv, "g1", rp->r_g1);
1855 PANICNVADD(pnv, "g2", rp->r_g2);
1856 PANICNVADD(pnv, "g3", rp->r_g3);
1857 PANICNVADD(pnv, "g4", rp->r_g4);
1858 PANICNVADD(pnv, "g5", rp->r_g5);
1859 PANICNVADD(pnv, "g6", rp->r_g6);
1860 PANICNVADD(pnv, "g7", rp->r_g7);
1861 PANICNVADD(pnv, "o0", rp->r_o0);
1862 PANICNVADD(pnv, "o1", rp->r_o1);
1863 PANICNVADD(pnv, "o2", rp->r_o2);
1864 PANICNVADD(pnv, "o3", rp->r_o3);
1865 PANICNVADD(pnv, "o4", rp->r_o4);
1866 PANICNVADD(pnv, "o5", rp->r_o5);
1867 PANICNVADD(pnv, "o6", rp->r_o6);
1868 PANICNVADD(pnv, "o7", rp->r_o7);
1869 PANICNVADD(pnv, "pc", (ulong_t)rp->r_pc);
1870 PANICNVADD(pnv, "npc", (ulong_t)rp->r_npc);
1871 PANICNVADD(pnv, "y", (uint32_t)rp->r_y);