Lines Matching refs:rd
78 uint_t rd, rs1, rs2;
97 rd = (inst >> 25) & 0x1f;
121 if (rd == 0)
123 else if (rd == 1)
138 if ((rd & 1) == 1)
139 rd = (rd & 0x1e) | 0x20;
140 rd = rd >> 1;
141 if ((sz == 16) && ((rd & 0x1) != 0))
217 printf("rd = %d, op3 = 0x%x, rs1 = %d, rs2 = %d, imm13=0x%x\n",
218 rd, op3, rs1, rs2, (inst & 0x1fff));
282 (unsigned *)&data.i[1], rd);
286 &data.l[0], rd);
289 &data.l[1], rd+1);
302 fpu_fr.fpu_regs[rd];
306 fp->fpu_fr.fpu_dregs[rd];
309 fp->fpu_fr.fpu_dregs[rd+1];
314 if (getreg(rp, rd, &data.l[0], badaddr))
316 if (getreg(rp, rd+1, &data.l[1], badaddr))
332 if (getreg(rp, rd, &data.l[0], badaddr))
505 (unsigned *)&data.i[1], rd);
508 &data.l[0], rd);
511 &data.l[1], rd+1);
518 fp->fpu_fr.fpu_regs[rd] =
521 fp->fpu_fr.fpu_dregs[rd] =
524 fp->fpu_fr.fpu_dregs[rd+1] =
544 if (putreg(&data.l[0], rp, rd, badaddr) == -1)
546 if (putreg(&data.l[1], rp, rd+1, badaddr) == -1)
549 if (putreg(&data.l[0], rp, rd, badaddr) == -1)
564 uint_t rd, rs1, rs2;
581 rd = (inst >> 25) & 0x1f;
672 if (getreg(rp, rd, &reven, badaddr))
674 if (getreg(rp, rd+1, &rodd, badaddr))
705 if (putreg(&reven, rp, rd, badaddr) == -1)
707 if (putreg(&rodd, rp, rd+1, badaddr) == -1)
720 uint_t rd, rs2, rs1;
724 rd = (inst >> 25) & 0x1f;
753 if (putreg(&cnt, rp, rd, badaddr) == -1)
767 uint_t rd, rs1;
829 rd = (inst >> 25) & 0x1f;
830 if (putreg(&ud64, rp, rd, badaddr)) {
848 uint_t rs1, rd;
887 rd = (inst >> 25) & 0x1f;
965 if (rd == 0 && !(i == 0 && ignor))
967 if (rd)
984 if ((op3 == IOP_V8_RETT && rd) ||
992 if (rd == 0)
1068 if (rd == 0 && !(i == 0 && ignor))
1070 if (rd)
1142 * Simulate a "rd %tick" or "rd %stick" (%asr24) instruction.
1147 uint_t inst, op, op3, rd, rs1, i;
1152 rd = (inst >> 25) & 0x1F;
1167 if (putreg(&tick, rp, rd, &badaddr) == 0)
1173 if (putreg(&stick, rp, rd, &badaddr) == 0)
1316 uint_t rd, rs1, rs2;
1328 rd = (inst >> 25) & 0x1f;
1346 if ((rd & 1) == 1)
1347 rd = (rd & 0x1e) | 0x20;
1348 rd = rd >> 1;
1422 uint_t rd, rs1, rs2;
1447 rd = (inst >> 25) & 0x1f;
1473 if (rd == 0)