Lines Matching refs:Tmp
68 #define Tmp %l7 /* general scratch */
89 ldn [Fdc + FD_NEXT], Tmp ! Try next ctlr...
90 tst Tmp
92 mov Tmp, Fdc
125 1: ldub [Reg], Tmp ! get csr
126 andcc Tmp, RQM, %g0 !
128 andcc Tmp, NDM, %g0 ! NDM set means data
130 andcc Tmp, DIO, %g0 ! check for input vs. output data
133 ldub [Reg + 0x1], Tmp ! DIO set, *addr = *fifo
135 stb Tmp, [Adr] !
136 2: ldsb [Adr], Tmp ! *fifo = *addr
137 stb Tmp, [Reg + 0x1] !
173 ldub [Adr], Tmp
174 or Tmp, Tmp2, Tmp
175 stb Tmp, [Adr]
181 andn Tmp, Tmp2, Tmp
182 stb Tmp, [Adr]
187 mov 3, Tmp
189 stb Tmp, [Fdc + FD_OPMODE]
195 mov 0x3, Tmp
197 stb Tmp, [Fdc + FD_OPMODE]
203 ldub [Reg], Tmp ! Tmp = *csr
204 1: andcc Tmp, CB, %g0 ! is CB set?
206 ldub [Reg], Tmp !! Tmp = *csr
210 1: andcc Tmp, RQM, %g0 !
212 ldub [Reg], Tmp ! busy wait until RQM set
213 mov SNSISTAT, Tmp ! cmd for SENSE_INTERRUPT_STATUS
214 stb Tmp, [Reg + 0x1]
218 ldub [Reg], Tmp ! busy wait until RQM set
219 1: andcc Tmp, RQM, Tmp
221 ldub [Reg], Tmp ! busy wait until RQM set
225 ldub [Reg + 0x1], Tmp
226 stb Tmp, [Fdc + FD_RSLT]
227 ldub [Reg], Tmp ! busy wait until RQM set
228 1: andcc Tmp, RQM, Tmp
230 ldub [Reg], Tmp ! busy wait until RQM set
234 ldub [Reg + 0x1], Tmp
236 stb Tmp, [Fdc + FD_RSLT + 1]
246 ldub [Reg], Tmp !
247 1: andcc Tmp, CB, %g0 ! is CB set?
249 andcc Tmp, RQM, %g0 ! check for RQM in delay slot
251 ldub [Reg], Tmp ! and load control reg in delay
252 andcc Tmp, DIO, %g0 ! DIO set?
254 ldub [Reg], Tmp ! and load control reg in delay
259 ldub [Reg + 0x1], Tmp ! *fifo into Tmp
262 ldub [Reg], Tmp ! and load control reg in delay
263 stb Tmp, [Adr] ! store new byte
266 ldub [Reg], Tmp ! and load control reg in delay
276 ldub [Fdc + FD_FASTTRAP], Tmp
277 tst Tmp
301 mov 0x4, Tmp
302 stb Tmp, [Fdc + FD_OPMODE]
315 ld [Adr], Tmp
316 inc Tmp
317 st Tmp, [Adr]
336 mov 0x4, Tmp
337 stb Tmp, [Fdc + FD_OPMODE]