Lines Matching refs:Reg
64 #define Reg %l4 /* pointer to the chip's registers */
107 ldn [Fdc + FD_REG], Reg ! load pointer to h/w registers
110 ldn [Fdc + FD_REG], Reg ! load pointer to h/w registers
125 1: ldub [Reg], Tmp ! get csr
133 ldub [Reg + 0x1], Tmp ! DIO set, *addr = *fifo
137 stb Tmp, [Reg + 0x1] !
203 ldub [Reg], Tmp ! Tmp = *csr
206 ldub [Reg], Tmp !! Tmp = *csr
212 ldub [Reg], Tmp ! busy wait until RQM set
214 stb Tmp, [Reg + 0x1]
218 ldub [Reg], Tmp ! busy wait until RQM set
221 ldub [Reg], Tmp ! busy wait until RQM set
225 ldub [Reg + 0x1], Tmp
227 ldub [Reg], Tmp ! busy wait until RQM set
230 ldub [Reg], Tmp ! busy wait until RQM set
234 ldub [Reg + 0x1], Tmp
246 ldub [Reg], Tmp !
251 ldub [Reg], Tmp ! and load control reg in delay
254 ldub [Reg], Tmp ! and load control reg in delay
259 ldub [Reg + 0x1], Tmp ! *fifo into Tmp
262 ldub [Reg], Tmp ! and load control reg in delay
266 ldub [Reg], Tmp ! and load control reg in delay