Lines Matching refs:Fdc
65 #define Fdc %l3 /* pointer to fdctlr structure */
78 set fdctlrs, Fdc ! load list of controllers
79 ldn [Fdc], Fdc ! get the first in the list...
80 1: tst Fdc ! do we have any more to check
84 3: ldub [Fdc + FD_OPMODE], Tmp2 ! load opmode into Tmp2
89 ldn [Fdc + FD_NEXT], Tmp ! Try next ctlr...
92 mov Tmp, Fdc
101 add Fdc, FD_HILOCK, %l6
107 ldn [Fdc + FD_REG], Reg ! load pointer to h/w registers
110 ldn [Fdc + FD_REG], Reg ! load pointer to h/w registers
116 ld [Fdc + FD_RLEN], Len
120 ldn [Fdc + FD_RADDR], Adr
146 4: st Len, [Fdc + FD_RLEN]
148 stn Adr, [Fdc + FD_RADDR]
157 st Len, [Fdc + FD_RLEN]
158 6: stn Adr, [Fdc + FD_RADDR]
171 ldn [Fdc + FD_AUXIOVA], Adr
172 ldub [Fdc + FD_AUXIODATA], Tmp2
180 ldub [Fdc + FD_AUXIODATA2], Tmp2
189 stb Tmp, [Fdc + FD_OPMODE]
193 7: st Len, [Fdc + FD_RLEN]
194 stn Adr, [Fdc + FD_RADDR]
197 stb Tmp, [Fdc + FD_OPMODE]
226 stb Tmp, [Fdc + FD_RSLT]
236 stb Tmp, [Fdc + FD_RSLT + 1]
244 add Fdc, FD_RSLT, Adr ! load address of csb->csb_rslt
276 ldub [Fdc + FD_FASTTRAP], Tmp
302 stb Tmp, [Fdc + FD_OPMODE]
311 ldn [Fdc + FD_HIINTCT], Adr
324 add Fdc, FD_HILOCK, %l6
337 stb Tmp, [Fdc + FD_OPMODE]
343 ldn [Fdc + FD_SOFTID], %o0